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PLX 9052 EEPROM 内容示例

楼主#
更多 发布于:2004-09-19 14:28
echo PLX 9052 EEPROM
echo by WANGKUI

eep  0 905010b5 echo PCIIDR; Device ID, Vendor ID
eep  4 06800002 echo PCICCR; Class Code
eep  8 905010b5 echo Subsystem ID, Subsystem Vendor ID
eep  c 00000100 echo Maximum Latency, Minimum Grant, Int Pin, Int Routing
eep 10 fffe0000 echo LAS0RR; Local Address Space 0 Range
eep 14 ffffff01 echo LAS1RR; Local Address Space 1 Range
eep 18 fffffff1 echo LAS2RR; Local Address Space 2 Range
eep 1c 00000000 echo LAS3RR; Local Address Space 3 Range
eep 20 00000000 echo EROMRR; Expansion ROM Range
eep 24 00000001 echo LAS0BA; Local Address Space 0 Base Address (Re-Map)
eep 28 000f0001 echo LAS1BA; Local Address Space 1 Base Address (Re-Map)
eep 2c 000ffff1 echo LAS2BA; Local Address Space 2 Base Address (Re-Map)
eep 30 00000000 echo LAS3BA; Local Address Space 3 Base Address (Re-Map)
eep 34 00000000 echo EROMBA; Expansion ROM Base Address (Re-Map)
eep 38 000000a2 echo LAS0BRD; Local Address Space 0 Bus Region Descriptors
eep 3c 00400022 echo LAS1BRD; Local Address Space 1 Bus Region Descriptors
eep 40 00400022 echo LAS2BRD; Local Address Space 2 Bus Region Descriptors
eep 44 00000000 echo LAS3BRD; Local Address Space 3 Bus Region Descriptors
eep 48 00000000 echo EROMBRD; Expansion ROM Bus Region Descriptors
eep 4c 00010001 echo CS0BASE; Chip Select 0 Base
eep 50 000f0081 echo CS1BASE; Chip Select 1 Base
eep 54 00000000 echo CS2BASE; Chip Select 2 Base
eep 58 00000000 echo CS3BASE; Chip Select 3 Base
eep 5c 00000039 echo INTCSR; Interrupt Control/Status
eep 60 00200003 echo CNTRL; User I/O, EEPROM, Init Control

echo Done!

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cici0505
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沙发#
发布于:2004-09-20 10:22
呵呵,支持楼主的这种精神!!!
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