谁帮我看看VHDL语法的问题

代码如下，打“->”的地方出错，“Subprogram error: can\'t interpret subprogram call”，我手上没什么太好的语法的书，所以查不出到底什么问题，请诸位帮忙看看。
谢谢！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_24bit is
port ( a, b : in std_logic;
up_dn_o,upclk1_o,dnclk1_o : out std_logic;
count_o : out bit_vector(7 downto 0));
end counter_24bit;

architecture behave of counter_24bit is
signal upclk1 : std_logic;
signal dnclk1 : std_logic;
signal upclk2 : std_logic;
signal upclk4 : std_logic;
signal dnclk2 : std_logic;
signal dnclk4 : std_logic;
signal up_dn : std_logic :=\'1\';
signal gen_clk : std_logic;
signal count : bit_vector(7 downto 0);
begin
upclk1 <= not(((a XOR b) and b) and up_dn);
dnclk1 <= (a or b) or up_dn;
gen_clk <= upclk1 and dnclk1;
up_dn_o <= up_dn;
upclk1_o <= upclk1;
dnclk1_o <= dnclk1;
count_o <= count;
process (a,b)
begin
if(a\'event and a = \'0\') then
if(b = \'1\') then
up_dn <= \'1\';
else
up_dn <= \'0\';
end if;
end if;
end process;
process (gen_clk,up_dn)
begin
if( gen_clk\'event and gen_clk = \'0\' ) then
if( up_dn = \'1\') then
if ( count = \"11111111\" ) then
count <= \"00000000\";
else
-> count <= count + \'1\';
end if;
else
if( count = \"00000000\" ) then
count <= \"11111111\";
else
-> count <= count - \'1\';
end if;
end if;
end if;
end process;
end behave;

VARIABLE direction : INTEGER range -1 to 1;

谢谢各位！
那部分的代码我改成：
PROCESS (gen_clk)
VARIABLE cnt : INTEGER RANGE -32767 TO 32767 := 0;
VARIABLE direction : INTEGER;
BEGIN
IF (up_dn = \'1\') THEN
direction := 1;
ELSE
direction := -1;
END IF;

IF (gen_clk\'EVENT AND gen_clk = \'1\') THEN
cnt := cnt + direction;
END IF;

count_o <= cnt;

END PROCESS;
中间direction是个整形，其实它的值也就是+1和-1，编译以后是不是会很浪费资源啊？

忘了，开头还要加上
use ieee.numeric_std.all;


我试过了，能编译通过，但你原来的也能编译没错呀。

类型不匹配，改成
count <= std_logic_vector(unsigned(count)-1)
 :P :cool:

对，应该是双引号，如果你写成COUNT+1也可以，只是要添加库，具体你可以查一下

是不是就是把\'1\'改成1啊，我试了，还是一样啊！

改的还有：
count_o : out STD_LOGIC_VECTOR(7 downto 0));
....
signal count : STD_LOGIC_VECTOR(7 DOWNTO 0);

你可以把上面的代码全部复制过去再编译。


[编辑 -  12/11/02 by  czja]

类型不匹配，COUNT为LTD_LOGIC_VECTOR,\'1\'为LTD_LOGIC,你改成
COUNT+\'00000001\'试试看

可以\'00000001\'吗？是不是\"00000001\"啊？这个我也试了，也还是不行。现在用maxplus带的加减法计数器例子改了，但我感觉占用了更多资源了。

类型不匹配，COUNT为LTD_LOGIC_VECTOR,\'1\'为LTD_LOGIC,你改成
COUNT+\'00000001\'试试看

是不是就是把\'1\'改成1啊，我试了，还是一样啊！

下面的代码可以编译，试试看。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--USE IEEE.STD_LOGIC_ARITH.ALL;

entity counter_24bit is
port ( a, b : in std_logic;
up_dn_o,upclk1_o,dnclk1_o : out std_logic;
count_o : out STD_LOGIC_VECTOR(7 downto 0));
end counter_24bit;

architecture behave of counter_24bit is
signal upclk1 : std_logic;
signal dnclk1 : std_logic;
signal upclk2 : std_logic;
signal upclk4 : std_logic;
signal dnclk2 : std_logic;
signal dnclk4 : std_logic;
signal up_dn : std_logic :=\'1\';
signal gen_clk : std_logic;
signal count : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
upclk1 <= not(((a XOR b) and b) and up_dn);
dnclk1 <= (a or b) or up_dn;
gen_clk <= upclk1 and dnclk1;
up_dn_o <= up_dn;
upclk1_o <= upclk1;
dnclk1_o <= dnclk1;
count_o <= count;
process (a,b)
begin
if(a\'event and a = \'0\') then
if(b = \'1\') then
up_dn <= \'1\';
else
up_dn <= \'0\';
end if;
end if;
end process;
process (gen_clk,up_dn)
begin
if( gen_clk\'event and gen_clk = \'0\' ) then
if( up_dn = \'1\') then
if ( count = \"11111111\" ) then
count <= \"00000000\";
else
count <= count+1;
end if;
else
if( count = \"00000000\" ) then
count <= \"11111111\";
else
count <= count-1;
end if;
end if;
end if;
end process;
end behave;