高手指导！

Class Document Source Message Time Date No.

[Error] BCD8.SCHDOC(98) VHDL Simulator ($C0007) : Unbound instance U1 of component BUFGS 11:53:59 AM 2003-12-9 8
[Error] TestBCD.VHDTST(63) VHDL Simulator ($C0049) : Syntax error: Not expecting [out] skipping input up to [end]. 12:07:42 PM 2003-12-9 11
请问是什么错误阿