200分，快崩溃了，还是系统DMA的启动问题

以前研究了一段时间的ISA的系统DMA的驱动，因为方案的变化，不采用DMA，现在采用基本的I/O传输，速率有点跟不上，想变成DMA，还得重新看。
我详细地看了《WINDOWS NT设备驱动程序设计指南》，（Art Baker 著），里面对系统DMA进行了详细的描述，在适配器控制例程里，利用IoMapTransfer对DMA控制器（8237）进行编程，相当于用汇编给8237的各寄存器写数据，所以，主板上的8237，驱动开发者是不能直接操作的。然后，书上说：给设备发送合适的命令来启动DMA的操作，在这里，我卡住了，我的设备是个FIFO，当FIFO半满的时候发DMA请求信号DREQ给总线，8237获得总线控制权后给FIFO发DMA应答信号DACK，怎么来启动DMA的操作？？外设没有什么中断控制寄存器，或者DMA使能寄存器等给我写，我怎么办？？

你的卡是一上电，就不停的采集数据吗？总有个命令才开始采集吧？然后FIFO才能半满吧？

你的卡是一上电，就不停的采集数据吗？总有个命令才开始采集吧？然后FIFO才能半满吧？
 

不是的，我的数据流向是从主板到板卡，也就是我要把电脑上应用层处理好后的数据传给驱动，通过DMA方式，驱动传给板子上的FIFO。

哦，sorry。

那你的FIFO等着半满才请求DMA，然而要有DMA你的FIFO才会有数据。呵呵。你不觉得有些问题吗？
FIFO半满请求DMA应该是为了把数据送到主机去。所以我总是想着你的数据是卡-->主机。

数据从主机到板卡，
那应该是8237A发DREQ，板卡回DACK#呀。

数据从主机到板卡，
那应该是8237A发DREQ，板卡回DACK#呀。
 

这位大哥说的不对吧？DREQ这个信号线是输入的，DACK是输出的。

哦，sorry。

那你的FIFO等着半满才请求DMA，然而要有DMA你的FIFO才会有数据。呵呵。你不觉得有些问题吗？
FIFO半满请求DMA应该是为了把数据送到主机去。所以我总是想着你的数据是卡-->主机。

非常地对不起，以前没有说清楚，我的数据传输方向是从主机到板卡上的FIFO。所以应当是FIFO空的时候发给总线DREQ。

你的卡是一上电，就不停的送出数据吗？总有个命令才开始送吧？然后FIFO才能空吧？

呵呵

你的卡是一上电，就不停的送出数据吗？总有个命令才开始送吧？然后FIFO才能空吧？

呵呵
 

是的，就是你说的这样，送出数据正是通过DMA方式啊。
我的板子上的 FIFO和一个单片机连接，开始的时候，FIFO肯定是空的，就给总线发DREQ，就是这个命令啊，没有其他的了！

一上电就送数据？不会吧？

[quote]数据从主机到板卡，
那应该是8237A发DREQ，板卡回DACK#呀。
 

这位大哥说的不对吧？DREQ这个信号线是输入的，DACK是输出的。 [/quote]
对不起，我搞错了。
回去查一下书，明天再和你讨论。

[quote][quote]数据从主机到板卡，
那应该是8237A发DREQ，板卡回DACK#呀。
 

这位大哥说的不对吧？DREQ这个信号线是输入的，DACK是输出的。 [/quote]
对不起，我搞错了。
回去查一下书，明天再和你讨论。 [/quote]

好的，谢谢你的关注！
如果是用汇编写程序直接来操作8237的寄存器，我想应该是没什么难度的。可是，现在是要在DDK的基础上，来操作8237，就是DDK的函数执行的过程中，就相当于给8237的寄存器写入了数值，我所能控制的只有外部设备。

以前一直没有实做过ISA的DMA，呵呵，不懂装懂，就出了问题。
昨天查了一下这方面的资料，觉得你的问题出在硬件。我把书中用软盘驱动器做DMA的一个例子贴在下面，然后再和你讨论。
以下文章摘自ISA System Architecture, Chapter 19.
今天早上冒着迟到的危险一字一字敲进电脑的，没翻译，呵呵。

[编辑 -  8/19/03 by  grant]

The DMAC used in ISA machines is the Intel 8237, providing four separate DMA channels. Two 8237s are used in a master/slave configuration, providing a total of seven DMA channels. Each DMA channel is used by a separate I/O device to handle block data transfers with memory.

Four distinct steps must occur to initiate and complete a DMA transfer.
1. Set up the DMA channel for the transfer.
2. Command the I/O device to initiate the block data transfer.
3. Grant the system buses to the DMA controller so it can run the bus cycle.
4. Notify the microprocessor that the transfer is complete.

Each DMA channel within the DMA controller has its own set of I/O register s that the programmer uses to set up the data transfer. The set of I/O registers associated with each DMA channel allows the programmer to specify:
1. The Transfer Count (number of DMA bus cycles to run).
2. The start memory address (start address in memory where data will be read from or written to).
3. the direction of transfer with reference to memory (type of transfer).

After the DMA channel has been set up by the programmer, the I/O device must be programmed to initiate the overall block data transfer. As an example, the programmer would issue the proper series of I/O write commands to a floppy disk controller to initiate a disk read operation.

Having set up the respective DMA channel and issued the proper commands to the I/O device (in this case, the floppy disk controller and DMA channel two), the microprocessor can then go on to another task. The entire data transfer and its termination will be handled by the I/O device and its respective DMA channel. The following paragraphs describe an example data transfer between system memory and a floppy disk controller.

When performing a floppy disk transfer, the programmer may only perform data transfers in multiples of the sector size. When running MS-DOS, a sector on a floppy disk contains 512 bytes of information. This would be the smallest data transfer possible when transferring information between a disk drive and memory.

1. The programmer issues a series of write to DMA channel two’s registers to set up the start memory address, transfer count and the direction of the transfer with reference to memory. In the disk read example, assume that the start memory address is 1000h, the transfer count  is 512 bytes (one sector) and that this is a write transfer (with reference to memory).
2. The floppy controller must be programmed with the disk read command, the cylinder number ,the head (or surface) number, the start sector number and the number of sectors to be read. In this example, we will assume a one sector (512 bytes) read from cylinder three, head one, sector five.
3. Upon receiving the parameters and the disk read command, the disk controller initiates a seek operation to position the read/write head mechanism over cylinder three. It must then wait for the disk to spin until the start of sector five is detected under the read head on surface one. As the disk is a mechanical device, this will take some time.

4. In the example of a read operation from a floppy disk controller, some time will elapse before the disk controller has read the first byte from disk.
5. When the first byte has been transferred from the disk to the disk controller, the floppy disk controller must then request that its associated DMA channel transfer the data. The floppy disk controller asserts DMA request line two (DIRQ2) that goes to the DMAC.
6. The DMAC responds by asserting its HRQ hold request output to seize the bus *address, data, and control buses) form the microprocessor. Since the refresh logic must also be able to seize the buses, the refresh logic also has a hold request output. These two hold request lines go to a tiny first-come-first-served arbiter which in turn drives the microprocessor’s HOLD request input.

7. Depending on the X86 microprocessor that is been used, the microprocessor will either complete the current bus cycle, complete the current instruction, or perform all the writes in its posted write buffer. Then the microprocessor will tri-state all of its bus output drivers, thereby floating the buses. The microprocessor also asserts HLDA to tell the requesting device (the DMAC in this case) that it is now the bus master. Logic on the system board asserts the ISA bus AEN signal when it sees HLDA asserted. Note that the ISA bus AEN signal is not the same as the DMAC AEN pin.
8. The DMAC then responds to DRQ2 from the disk controller by asserting DMA Acknowledge (DACK2#) and the I/O read command line (IORC#). These two lines go to the disk controller via the IDA bus.
9. The disk controller de-asserts DRQ2 and begins the access to the data register to place data onto the data bus.