请教PHILPS的7146的DEBI接口开发。

在我买来的卡上有DEBI接口，在98下，已经好用，但PHILPS没有提供2K的驱动，我写了该卡的简单驱动，图象现在出现了，但我试写DEBI接口，但怎么也不行，接口是简单方式，没有要求块传输，有搞过的老大请帮帮忙，谢谢。

一段简单的代码，供你参考
VOID DebiWrite(ULONG addr,ULONG value)
{
ULONG debicfg=0;
/*
7CH
XIRQ_EN 31 RW enable external interrupt on GPIO3
XRESUME 30 RW resume block transfer when XIRQ was de-asserted
- 29 - reserved
FAST    28 RW enable fast mode (short trwi time)
-     27 and 26 - reserved
TIMEOUT [3:0] 25 to 22 RW timer set-up value (PCI clock cycles)
SWAP 21 and 20 RW endian swap type:
00: straight - don’t swap
01: 2-byte swap
10: 4-byte swap
11: reserved
SLAVE16 19 RW indicates that slave is able to serve 16-bit cycles
INCREMENT 18 RW enables address increment for block transfer
INTEL 17 RW Intel style bus handshake if HIGH, else Motorola style
TIEN 16 RW timer enable (active LOW)
- 15 to 0 - reserved
*/
debicfg =   (0x0 <<  31 )   // XIRQ_EN;enable external interrupt on GPIO3
     | (0x1 <<  30 )   // XRESUME;resume block transfer when XIRQ was de-asserted
 | (0x0  << 29 )   // reserved ;
 | (0x1  << 28 )   // fast mode enable
 | (0x00 << 26 )   // reserved
 | (0x0 << 22 )   // timeout
 | (0x00 << 20 )   // endian swap type
 | (0x0  << 19 )   // slave16:indicates that slave is able to serve 16-bit cycles
 | (0x0  << 18 )   // increment
 | (0x1  << 17 )   // intel  Intel style bus handshake if HIGH, else Motorola style
 | (0x0  << 16 )   // timer enable (active low)
 | (0x0  );        // reserved

WriteReg(SAA7146_DEBI_CONFIG,debicfg);
/*
Table 96 DEBI_COMMAND
OFFSET NAME BIT TYPE DESCRIPTION
80H BLOCKLENGTH
[14:0]
31 to 17 RW BLOCKLENGTH > 4: block transfer length in bytes
4 3 BLOCKLENGTH > 0: immediate transfer 1 to 4 bytes
BLOCKLENGTH = 0: reserved
WRITE_N 16 RW transfer direction (write if LOW)
A16_IN 15 to 0 RW slave target start address
*/
ULONG debicmd;
debicmd=   ( 2 << 17 )  // block length
| ( 0x0  << 16 )  // write_n  transfer direction ( write if low)
|  addr;        // slave target start address;



WriteReg(SAA7146_DEBI_COMMAND,debicmd);

ULONG debiad;

/*
data input/output in immediate mode or DMA start address
for block transfer (Dword aligned, DEBI_AD [1:0] have to be
set to logic 0)
*/
debiad=value;
WriteReg(SAA7146_DEBI_AD,debiad);
/*
DEBI page table address (not used if PAGE_EN = 0)
PAGE_EN 11 RW enable address paging
- 10 to 0 - reserved
*/


WriteReg(SAA7146_DEBI_PAGE,0); // this is a test for debi transfer
  // and we alwal
ULONG t1,t2;

t1=ReadReg(SAA7146_PSR);
WriteReg(SAA7146_ISR,0x80000000);
t1=ReadReg(SAA7146_PSR);

WriteReg(SAA7146_MC2,
(
        ( SAA7146_MC2_UPLD_DEBI )
<< 16
)|0xFFFF
);
 }

/* Debi 读*/
ULONG  DebiRead(ULONG addr)
{
ULONG debicfg=0;
/*
7CH
XIRQ_EN 31 RW enable external interrupt on GPIO3
XRESUME 30 RW resume block transfer when XIRQ was de-asserted
- 29 - reserved
FAST    28 RW enable fast mode (short trwi time)
-     27 and 26 - reserved
TIMEOUT [3:0] 25 to 22 RW timer set-up value (PCI clock cycles)
SWAP 21 and 20 RW endian swap type:
00: straight - don’t swap
01: 2-byte swap
10: 4-byte swap
11: reserved
  19 RW indicates that slave is able to serve 16-bit cycles
INCREMENT 18 RW enables address increment for block transfer
INTEL 17 RW Intel style bus handshake if HIGH, else Motorola style
TIEN 16 RW timer enable (active LOW)
- 15 to 0 - reserved
*/
debicfg =   (0x0  <<  31 )   // XIRQ_EN;enable external interrupt on GPIO3
     | (0x1  <<  30 )   // XRESUME;resume block transfer when XIRQ was de-asserted
 | (0x0  << 29 )   // reserved ;
 | (0x0  << 28 )   // fast mode enable
 | (0x00 << 26 )   // reserved
 | (0x0  << 22 )   // timeout
 | (0x00 << 20 )   // endian swap type
 | (0x0  << 19 )   // slave16:indicates that slave is able to serve 16-bit cycles
 | (0x0  << 18 )   // increment
 | (0x1  << 17 )   // intel  Intel style bus handshake if HIGH, else Motorola style
 | (0x0  << 16 )   // timer enable (active low)
 | (0x0  );        // reserved

WriteReg(SAA7146_DEBI_CONFIG,debicfg);
/*
Table 96 DEBI_COMMAND
OFFSET NAME BIT TYPE DESCRIPTION
80H BLOCKLENGTH
[14:0]
31 to 17 RW BLOCKLENGTH > 4: block transfer length in bytes
4 3 BLOCKLENGTH > 0: immediate transfer 1 to 4 bytes
BLOCKLENGTH = 0: reserved
WRITE_N 16 RW transfer direction (write if LOW)
A16_IN 15 to 0 RW slave target start address
*/
ULONG debicmd;
debicmd=   ( 0x02 << 17 )  // block length
| ( 0x1  << 16 )  // write_n  transfer direction ( write if low)
|  addr;        // slave target start address;



WriteReg(SAA7146_DEBI_COMMAND,debicmd);

ULONG debiad;

/*
data input/output in immediate mode or DMA start address
for block transfer (Dword aligned, DEBI_AD [1:0] have to be
set to logic 0)
*/
/*
DEBI page table address (not used if PAGE_EN = 0)
PAGE_EN 11 RW enable address paging
- 10 to 0 - reserved
*/


WriteReg(SAA7146_DEBI_PAGE,0); // this is a test for debi transfer
  // and we alwal
ULONG t1,t2;
/*
t1=ReadReg(SAA7146_PSR);
WriteReg(SAA7146_ISR,0x80000000);
t1=ReadReg(SAA7146_PSR);
*/
WriteReg(SAA7146_MC2,
(
        ( SAA7146_MC2_UPLD_DEBI )
<< 16
)|0xFFFF
);
do
    {
t1=ReadReg(SAA7146_PSR);
}
while( t1 & SAA7146_PSR_DEBI_S == 1 );

    return ReadReg(SAA7146_DEBI_AD);

}

我用了你的方法，没有得到结果，我看我和你对DEBI的理解应该是一样的。如果你确认你用此方法成功的话，我看应该是硬件的事情了（）。

7146和7146a的DEBI接口有区别，要注意哦。

能否给的详细一点，不胜感激，谢谢。

你用debi是控制啥芯片，我要写saa7146控制zapex z1510,
可以交流一下