请教这段话该如何翻译

23以下的内容，我无法完全看懂。尤其是最后一句话不能完全理解

Table 3. Interrupt Control/Status Register
   Bit                                                

 31:24       Reserved. Always zero.

    23      

Interrupt asserted.This read-only status bit indicates
that one or more interrupt conditions is present. This
bit is the OR of the mailbox interrupt conditions described by bits 17 and 16,as well as the OR of the Add-On interrupt decripted in Bit 22(if the Add-On Interrupt is Enabled With Bit 13).No PCI interrupt is generated,nor is this bit is ever set,for an Add-On Interrupt without the Add-On Interrupt Enable set.


[编辑 -  4/15/05 by  limee]