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阅读：4482回复：14
编译NAND flash启动eboot的问题(ce 5.0)
我根据PB 5.0 自带的smdk2410 BSP中的代码修改自己的eboot，
这个代码本身是为NOR flash 启动设计的 我的系统中没有NOR flash 需要从NAND flash启动 但是我将编译生成的 eboot.nb0 写入flash后程序根本没有执行 检查该文件发现其前4k的空间仅有如下内容 00000000h: FE 03 00 EA 00 00 00 00 00 00 00 00 00 00 00 00 ; ?.?........... 00000010h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ; ................ 00000020h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ; ................ 00000030h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ; ................ 00000040h: 45 43 45 43 28 B6 06 8C 28 36 03 00 00 00 00 00 ; ECEC(??6...... 其余全为0x00 这就造成启动写入sram的代码尽有一条跳转指令 显然不可能启动 请问如何才能令生成的eboot.nb0将代码写入前4k空间？ 我目前仅修改了原PB自带代码的startup.s文件 其余配置文件未动 以下是boot.bib文件的内容 请大家看看有什么地方需要改动 MEMORY ; Name Start Size Type ; ------- -------- -------- ---- ARGS 8c020800 00000800 RESERVED RAM 8c026000 00006000 RAM STACK 8c02c000 00004000 RESERVED EBOOT 8c038000 00040000 RAMIMAGE ; Area used to cache nk.bin while programming flash FLSCACHE 8c200000 01400000 RESERVED DISPLAY 8c100000 00100000 RESERVED CONFIG COMPRESSION=OFF PROFILE=OFF KERNELFIXUPS=ON ROMOFFSET=25FC8000 SRE=ON ROMSTART=8c038000 ROMWIDTH=32 ROMSIZE=40000 MODULES ; Name Path Memory Type ; -------------- ---------------------------------------------- ----------- nk.exe $(_TARGETPLATROOT)\target\$(_TGTCPU)\$(WINCEDEBUG)\eboot.exe EBOOT |
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沙发#
发布于：2007-05-23 09:40
另外地址0x00000000的跳转似乎也有问题
在本映像中，0x03fe处附近的内容也是全为0x00 显然无法执行 下面贴上我starup.s的代码 希望能协助大家分析原因 ; ; Copyright (c) Microsoft Corporation. All rights reserved. ; ; ; Use of this source code is subject to the terms of the Microsoft end-user ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. ; If you did not accept the terms of the EULA, you are not authorized to use ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your ; install media. ; INCLUDE kxarm.h INCLUDE armmacros.s INCLUDE s3c2410x.inc ;------------------------------------------------------------------------------- MemoryMap EQU 0x2a4 BANK_SIZE EQU 0x00100000 ; 1MB per bank in MemoryMap array BANK_SHIFT EQU 20 ; Define RAM space for the Page Tables: ; PHYBASE EQU 0x30000000 ; physical start PTs EQU 0x30010000 ; 1st level page table address (PHYBASE + 0x10000) ; save room for interrupt vectors. ;------------------------------------------------------------------------------- TEXTAREA IMPORT main ; Set up the MMU and Dcache for bootloader. ; ; This routine will initialize the first-level page table based up the contents ; of the MemoryMap array and enable the MMU and caches. ; ; Copy the image to RAM if it's not already running there. ; ; Include Files ; Defines ;------------------------------------------------------------------------------ ; BUGBUG - ? PLLVAL EQU (((0xa1 << 12) + (0x3 << 4) + 0x1)) ;------------------------------------------------------------------------------ ; Cache Configuration DCACHE_LINES_PER_SET_BITS EQU (6) DCACHE_LINES_PER_SET EQU (64) DCACHE_NUM_SETS EQU (8) DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS) DCACHE_LINE_SIZE EQU (32) ;------------------------------------------------------------------------------ ; Sleep state constants ; ; Location of sleep data ; BUGBUG - this needs to be declared as a local var. SLEEPDATA_BASE_PHYSICAL EQU 0x30058000 ; Sleep State memory locations SleepState_Data_Start EQU (0) SleepState_WakeAddr EQU (SleepState_Data_Start + 0) SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE) SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE) SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE) SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE) SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE) SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE) SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE) SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE) SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE) SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE) SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE) SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE) SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE) SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE) SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE) SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE) SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE) SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE) SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE) SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE) SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE) SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE) SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE) SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE) SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE) SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4 ; External Variables ; External Functions ; Global Variables ; Local Variables ; Local Functions ;------------------------------------------------------------------------------- ; Function: Startup ; ; Main entry point for CPU initialization. ; STARTUPTEXT LEAF_ENTRY StartUp ; Jump over power-off code. b ResetHandler ; Power-off the CPU. str r1, [r0] ; enable SDRAM self-refresh. str r3, [r2] ; MISCCR setting. str r5, [r4] ; POWER OFF!!!!! b . ResetHandler ; Make sure that TLB & cache are consistent mov r0, #0 mcr p15, 0, r0, c8, c7, 0 ; flush both TLB mcr p15, 0, r0, c7, c5, 0 ; invalidate instruction cache mcr p15, 0, r0, c7, c6, 0 ; invalidate data cache ldr r0, = GPFCON ldr r1, = 0x55aa str r1, [r0] ldr r0, = GPFDAT ldr r1, = 0x10 str r1, [r0] ldr r0, = WTCON ; disable watch dog ldr r1, = 0x0 str r1, [r0] ldr r0, = INTMSK ldr r1, = 0xffffffff ; disable all interrupts str r1, [r0] ldr r0, = INTSUBMSK ldr r1, = 0x7ff ; disable all sub interrupt str r1, [r0] ldr r0, = INTMOD mov r1, #0x0 ; set all interrupt as IRQ str r1, [r0] ldr r0, = CLKDIVN ldr r1, = 0x3 ; 0x0 = 1:1:1, 0x1 = 1:1:2 ; 0x2 = 1:2:2, 0x3 = 1:2:4, ; 0x8 = 1:4:4 str r1, [r0] ands r1, r1, #0x2 ; set AsyncBusMode beq %F10 mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #R1_nF:OR:R1_iA mcr p15, 0, r0, c1, c0, 0 10 ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register. ldr r1, = 0xffffff str r1, [r0] ldr r0, = MPLLCON ; Configure MPLL ; Fin=12MHz, Fout=50MHz ldr r1, = PLLVAL str r1, [r0] ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz ldr r1, = ((0x48 << 12) + (0x3 << 4) + 0x2) str r1, [r0] ldr r0, = GPFDAT ldr r1, = 0x20 str r1, [r0] mov r0, #0x2000 20 subs r0, r0, #1 bne %B20 ;------------------------------------------------------------------------------ ; Add for Power Management ldr r1, =GSTATUS2 ; Determine Booting Mode ldr r10, [r1] tst r10, #0x2 beq %F30 ; if not wakeup from PowerOffmode ; skip MISCCR setting ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0 ldr r0, [r1] ; I don't know why, Just fallow Sample Code. bic r0, r0, #(7 << 17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H str r0, [r1] 30 ;------------------------------------------------------------------------------ ; Initialize memory controller ldr r0, = GPFDAT ldr r1, = 0x30 str r1, [r0] add r0, pc, #MEMCTRLTAB - (. + 8) ldr r1, = BWSCON ; BWSCON Address add r2, r0, #52 ; End address of MEMCTRLTAB 40 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne %B40 ;------------------------------------------------------------------------------ ; Add for Power Management ldr r0, = GPFDAT ldr r1, = 0x40 str r1, [r0] tst r10, #0x2 beq BringUpWinCE ; Normal Mode Booting ldr r0, = GPFDAT ldr r1, = 0x50 str r1, [r0] ;------------------------------------------------------------------------------ ; Recover Process : Starting Point ; ; 1. Checksum Calculation saved Data ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure mov r3, r5 ; pointer for checksum calculation mov r2, #0 ldr r0, =SLEEPDATA_SIZE ; get size of data structure to do checksum on 50 ldr r1, [r3], #4 ; pointer to SLEEPDATA and r1, r1, #0x1 mov r1, r1, LSL #31 orr r1, r1, r1, LSR #1 add r2, r2, r1 subs r0, r0, #1 ; dec the count bne %b50 ; loop till done ldr r0,=GSTATUS3 ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register teq r2, r3 ; compare to what we saved before going to sleep bne BringUpWinCE ; bad news - do a cold boot ; 2. MMU Enable ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info ldr r7, [r5, #SleepState_WakeAddr ] ; load the LR address nop nop nop nop nop ; if software reset mov r1, #0 teq r1, r7 bne %f60 bl BringUpWinCE ; wakeup routine 60 mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0 mcr p15, 0, r9, c2, c0, 0 ; PT address mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs mcr p15, 0, r8, c1, c0, 0 ; restore MMU control ; 3. Jump to Kernel Image's fw.s (Awake_address) mov pc, r7 ; jump to new VA (back up Power management stack) nop ;------------------------------------------------------------------------------ ; Add for Power Management ? BringUpWinCE ldr r0, = GPFDAT mov r1, #0x60 str r1, [r0] ;------------------------------------------------------------------------------ ; Copy boot loader to memory ands r9, pc, #0xFF000000 ; see if we are in flash or in ram bne %f20 ; go ahead if we are already in ram ; This is the loop that perform copying. ldr r0, = 0x38000 ; offset into the RAM add r0, r0, #PHYBASE ; add physical base mov r1, r0 ; (r1) copy destination ldr r2, =0x4e000000 ;address of NFCON ldr r3, =0x4e000004 ;NFCMD ldr r4, =0x4e000008 ;NFADDR ldr r5, =0x4e00000c ;NFDATA ldr r6, =0x4e000010 ;NFSTAT ldr r7, =0x4e000014 ;NFECC ldr r8, =0xff77 ;Set mode of NAND flash str r8, [r2] ldr r8, =0xf777 ;set nCE to low str r8, [r2] ldr r8, =0xff ;RESET str r8, [r3] ldr r9, =0x200 ; counter of page(0x40000/0x200) ldr r10, =0x00 ; addr1 ldr r11, =0x00 ; addr2 10 ldr r8, [r6] cmp r8,#0x01 beq %b10 ; wait when flash is busy ldr r8, =0x00 ; read1 command str r8, [r3] ldr r8, =0x00 str r8, [r4] str r10, [r4] str r11, [r4] str r8, [r4] ldr r12, =0x200 ;byte count of one page 15 ldr r8, [r6] cmp r8,#0x01 beq %b15 ; wait when flash is busy 18 ldr r8, [r5] ;read data str r8, [r1], #4 ;copy to ram subs r12, r12, #1 bne %b18 add r10, r10, #0x01 cmp r10, #0x100 bne %f19 add r11, r11, #0x01 19 subs r9, r9, #0x01 bne %b10 ; Restart from the RAM position after copying. mov pc, r0 nop nop nop nop nop nop ; Shouldn't get here. b . INCLUDE oemaddrtab_cfg.inc ; Compute physical address of the OEMAddressTable. 20 add r11, pc, #g_oalAddressTable - (. + 8) ldr r10, =PTs ; (r10) = 1st level page table ; Setup 1st level page table (using section descriptor) ; Fill in first level page table entries to create "un-mapped" regions ; from the contents of the MemoryMap array. ; ; (r10) = 1st level page table ; (r11) = ptr to MemoryMap array add r10, r10, #0x2000 ; (r10) = ptr to 1st PTE for "unmapped space" mov r0, #0x0E ; (r0) = PTE for 0: 1MB cachable bufferable orr r0, r0, #0x400 ; set kernel r/w permission 25 mov r1, r11 ; (r1) = ptr to MemoryMap array 30 ldr r2, [r1], #4 ; (r2) = virtual address to map Bank at ldr r3, [r1], #4 ; (r3) = physical address to map from ldr r4, [r1], #4 ; (r4) = num MB to map cmp r4, #0 ; End of table? beq %f40 ldr r5, =0x1FF00000 and r2, r2, r5 ; VA needs 512MB, 1MB aligned. ldr r5, =0xFFF00000 and r3, r3, r5 ; PA needs 4GB, 1MB aligned. add r2, r10, r2, LSR #18 add r0, r0, r3 ; (r0) = PTE for next physical page 35 str r0, [r2], #4 add r0, r0, #0x00100000 ; (r0) = PTE for next physical page sub r4, r4, #1 ; Decrement number of MB left cmp r4, #0 bne %b35 ; Map next MB bic r0, r0, #0xF0000000 ; Clear Section Base Address Field bic r0, r0, #0x0FF00000 ; Clear Section Base Address Field b %b30 ; Get next element 40 tst r0, #8 bic r0, r0, #0x0C ; clear cachable & bufferable bits in PTE add r10, r10, #0x0800 ; (r10) = ptr to 1st PTE for "unmapped uncached space" bne %b25 ; go setup PTEs for uncached space sub r10, r10, #0x3000 ; (r10) = restore address of 1st level page table ; Setup mmu to map (VA == 0) to (PA == 0x30000000). ldr r0, =PTs ; PTE entry for VA = 0 ldr r1, =0x3000040E ; uncache/unbuffer/rw, PA base == 0x30000000 str r1, [r0] ; uncached area. add r0, r0, #0x0800 ; PTE entry for VA = 0x0200.0000 , uncached ldr r1, =0x30000402 ; uncache/unbuffer/rw, base == 0x30000000 str r1, [r0] ; Comment: ; The following loop is to direct map RAM VA == PA. i.e. ; VA == 0x30XXXXXX => PA == 0x30XXXXXX for S3C2400 ; Fill in 8 entries to have a direct mapping for DRAM ; ldr r10, =PTs ; restore address of 1st level page table ldr r0, =PHYBASE add r10, r10, #(0x3000 / 4) ; (r10) = ptr to 1st PTE for 0x30000000 add r0, r0, #0x1E ; 1MB cachable bufferable orr r0, r0, #0x400 ; set kernel r/w permission mov r1, #0 mov r3, #64 45 mov r2, r1 ; (r2) = virtual address to map Bank at cmp r2, #0x20000000:SHR:BANK_SHIFT add r2, r10, r2, LSL #BANK_SHIFT-18 strlo r0, [r2] add r0, r0, #0x00100000 ; (r0) = PTE for next physical page subs r3, r3, #1 add r1, r1, #1 bgt %b45 ldr r10, =PTs ; (r10) = restore address of 1st level page table ; The page tables and exception vectors are setup. ; Initialize the MMU and turn it on. mov r1, #1 mcr p15, 0, r1, c3, c0, 0 ; setup access to domain 0 mcr p15, 0, r10, c2, c0, 0 mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs mov r1, #0x0071 ; Enable: MMU orr r1, r1, #0x0004 ; Enable the cache ldr r0, =VirtualStart cmp r0, #0 ; make sure no stall on "mov pc,r0" below mcr p15, 0, r1, c1, c0, 0 mov pc, r0 ; & jump to new virtual address nop ; MMU & caches now enabled. ; (r10) = physcial address of 1st level page table ; VirtualStart mov sp, #0x8C000000 add sp, sp, #0x30000 ; arbitrary initial super-page stack pointer b main ENTRY_END LTORG ;------------------------------------------------------------------------------ ; Memory Controller Configuration ; ; The below defines are used in the MEMCTRLTAB table ; defined below to iniatialize the memory controller's ; register bank. ; ; SDRAM refresh control register configuration REFEN EQU (0x1) ; Refresh enable TREFMD EQU (0x0) ; CBR(CAS before RAS)/Auto refresh Trp EQU (0x0) ; 2clk Trc EQU (0x3) ; 7clk Tchr EQU (0x2) ; 3clk REFCNT EQU (1113) ; period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) ; Bank Control ; ; Bus width and wait status control B1_BWSCON EQU (DW32) B2_BWSCON EQU (DW16) B3_BWSCON EQU (DW16 + WAIT + UBLB) B4_BWSCON EQU (DW16) B5_BWSCON EQU (DW16) B6_BWSCON EQU (DW32) B7_BWSCON EQU (DW32) ; Bank 0 B0_Tacs EQU (0x0) ; 0clk B0_Tcos EQU (0x0) ; 0clk B0_Tacc EQU (0x7) ; 14clk B0_Tcoh EQU (0x0) ; 0clk B0_Tah EQU (0x0) ; 0clk B0_Tacp EQU (0x0) B0_PMC EQU (0x0) ; normal ; Bank 1 B1_Tacs EQU (0x0) ; 0clk B1_Tcos EQU (0x0) ; 0clk B1_Tacc EQU (0x7) ; 14clk B1_Tcoh EQU (0x0) ; 0clk B1_Tah EQU (0x0) ; 0clk B1_Tacp EQU (0x0) B1_PMC EQU (0x0) ; normal ; Bank 2 B2_Tacs EQU (0x0) ; 0clk B2_Tcos EQU (0x0) ; 0clk B2_Tacc EQU (0x7) ; 14clk B2_Tcoh EQU (0x0) ; 0clk B2_Tah EQU (0x0) ; 0clk B2_Tacp EQU (0x0) B2_PMC EQU (0x0) ; normal ; Bank 3 B3_Tacs EQU (0x0) ; 0clk B3_Tcos EQU (0x0) ; 0clk B3_Tacc EQU (0x7) ; 14clk B3_Tcoh EQU (0x0) ; 0clk B3_Tah EQU (0x0) ; 0clk B3_Tacp EQU (0x0) B3_PMC EQU (0x0) ; normal ; Bank 4 B4_Tacs EQU (0x0) ; 0clk B4_Tcos EQU (0x0) ; 0clk B4_Tacc EQU (0x7) ; 14clk B4_Tcoh EQU (0x0) ; 0clk B4_Tah EQU (0x0) ; 0clk B4_Tacp EQU (0x0) B4_PMC EQU (0x0) ; normal ; Bank 5 B5_Tacs EQU (0x0) ; 0clk B5_Tcos EQU (0x0) ; 0clk B5_Tacc EQU (0x7) ; 14clk B5_Tcoh EQU (0x0) ; 0clk B5_Tah EQU (0x0) ; 0clk B5_Tacp EQU (0x0) B5_PMC EQU (0x0) ; normal ; Bank 6 B6_MT EQU (0x3) ; SDRAM B6_Trcd EQU (0x1) ; 3clk B6_SCAN EQU (0x1) ; 9bit ; Bank 7 ; ; Note - there is no memory connected to Bank 7 B7_MT EQU (0x3) ; SDRAM B7_Trcd EQU (0x1) ; 3clk B7_SCAN EQU (0x1) ; 9bit ;------------------------------------------------------------------------------ ; Memory Controller Configuration Data Table ; ; This data block is loaded into the memory controller's ; registers to configure the platform memory. ; MEMCTRLTAB DATA DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ; BANKCON0 DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ; BANKCON1 DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ; BANKCON2 DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ; BANKCON3 DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ; BANKCON4 DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ; BANKCON5 DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ; BANKCON6 DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ; BANKCON7 DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ; REFRESH DCD 0xB2 ; BANKSIZE DCD 0x30 ; MRSRB6 DCD 0x30 ; MRSRB7 END ;------------------------------------------------------------------------------- |
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板凳#
发布于：2007-05-23 10:24
还有source文件的内容
TARGETNAME=eboot TARGETTYPE=PROGRAM RELEASETYPE=PLATFORM EXEENTRY=StartUp WINCECPU=1 NOMIPS16CODE=1 INCLUDES=$(INCLUDES);$(_PUBLICROOT)\common\oak\drivers\block\msflashfmd\inc ADEFINES=-pd "_TGTCPU SETS \"$(_TGTCPU)\"" $(ADEFINES) CDEFINES= $(CDEFINES) -DPPSH_PROTOCOL_NOTIMEOUT -DCOREDLL LDEFINES=-subsystem:native /DEBUG /DEBUGTYPE:CV /FIXED:NO TARGETLIBS= \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_memory_s3c2410x.lib \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_cache_s3c2410x.lib \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_rtc_s3c2410x.lib \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_kitl.lib \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_log.lib \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_blnk.lib \ $(_PLATCOMMONLIB)\$(_CPUINDPATH)\oal_blcommon.lib \ $(_COMMONOAKROOT)\lib\$(_CPUINDPATH)\eboot.lib \ $(_COMMONOAKROOT)\lib\$(_CPUINDPATH)\cs8900dbg.lib \ $(_COMMONOAKROOT)\lib\$(_CPUINDPATH)\ne2kdbg.lib \ $(_COMMONOAKROOT)\lib\$(_CPUINDPATH)\ddk_io.lib \ $(_TARGETPLATROOT)\lib\$(_CPUINDPATH)\smflash_lib.lib \ $(_COMMONOAKROOT)\lib\$(_CPUINDPATH)\fulllibc.lib SOURCES= \ startup.s \ util.s \ main.c \ debug.c \ ether.c \ flash.c \ am29lv800.c \ bitmap.c \ nand.c WINCETARGETFILES=BootImage |
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地板#
发布于：2007-05-25 13:22
2410自带的NAND启动功能只能启动4K扇区，EBoot对它来说显然太大了。你应该把SMDK所自带的体积很小的NBOOT程序烧写到NAND起始扇区，由NBOOT来装载EBOOT
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地下室#
发布于：2007-05-28 14:10
引用第3楼cyx77于2007-05-25 13:22发表的 : 虽然eboot很大，但是将代码从flash复制的内存的工作在startup.s中就可以完成，这部分做到4k以内是完全没问题的，所以并不需要nboot |
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5楼#
发布于：2007-05-28 17:30
问题是连接生成的EBOOT.NB0的有效指令是偏移0x1000之后开始的，所以做不了你想的。你可以尝试一下，直接把EBOOT.NB0前面0x1000截掉烧到NAND FLASH中去执行一下。我也一直没找到那儿指定这个编译地址0x1000的地方。
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6楼#
发布于：2007-05-29 08:47
引用第5楼zhengshijie于2007-05-28 17:30发表的 : 这也正是我目前遇到的问题和临时解决方案 但是仍有一定问题 在startup.s末尾 代码已经正确复制到SDRAM中 并且MMU也正确配置工作正常后 最后一步跳转到main的语句似乎执行不正确 目前还不能运行C语言部分的程序 原因暂时还不清楚 你这个方法看上去不错 回头我试试 |
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7楼#
发布于：2007-05-30 17:13
看了一下你的代码，有点地方也许可以改进一下，
; Restart from the RAM position after copying. mov pc, r0 这里的跳转最好是接到这里的后面的指令，而不是跳到头重新来一遍。 |
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8楼#
发布于：2007-05-31 15:20
引用第7楼zhengshijie于2007-05-30 17:13发表的 : CE本身带的从NOR flash启动的eboot代码就是这么写的 所以我也没改 |
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9楼#
发布于：2007-06-03 23:11
据称，前面的空白是因为编译器决定的，eboot和application使用共同的编译器。而application的前面是需要pe结构的。所以eboot被弄成那样子了。
直接去掉空白部分也是不可行的，因为把相对偏移地址改变了。 |
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10楼#
发布于：2007-06-07 13:56
引用第9楼high于2007-06-03 23:11发表的 : 应该不是这个问题 arm 指令集的地址应该都是用的相对地址的 整体偏移应该不会影响什么 要不把代码拷到内存就不能运行了 |
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11楼#
发布于：2007-06-08 19:48
引用第6楼xdwumin于2007-05-29 08:47发表的 : 你看看SP是不是设的不对,与其它的东西好像关系不大 |
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12楼#
发布于：2007-06-14 16:45
使用FS2410 BIOS就可以用USB下载NK了。其中的启动代码有从NAND FLASH搬运到SDRAM的。可以参考。
在网上搜一下就有BIOS的代码了。 |
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13楼#
发布于：2007-06-27 15:23
引用第11楼microsun于2007-06-08 19:48发表的 : 请问SP寄存器叫什么名字？设置上需要注意什么？ |
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14楼#
发布于：2007-07-04 08:14
sp,就叫SP,或者是R13
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