帮忙看看双口RAM程序

在下面的代码中 我如果把write2 的进程加入后 在MODELSIM中双口RAM的仿真读写就不正常了 如果去掉write2 的进程，读写就好，请问是什么原因 ，而且在synplify中编译（write2进程在程序中）会出现Assignment to signal under different clocks not supported
也就是write2进程的问题 。请大侠指点是什么原因 如何解决？
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

package ram_lib is  
  component ram_dp2
    port (reset :in  std_logic;
          wr1 :in  std_logic;
          wr2 :in  std_logic;
          we1 :in  std_logic;
          we2 :in  std_logic;
          addr1 :in  std_logic_vector (7 downto 0);
          addr2 :in  std_logic_vector (7 downto 0);
          din1 :in  std_logic_vector (7 downto 0);
          din2 :in  std_logic_vector (7 downto 0);
          dout1 :out std_logic_vector (7 downto 0);
          dout2 :out std_logic_vector (7 downto 0));
  end component;
  function slv_to_integer(x : std_logic_vector)
       return integer;
  function integer_to_slv(n, bits : integer)
      return std_logic_vector;  
end ram_lib;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

package body ram_lib is
  function slv_to_integer(x : std_logic_vector)
       return integer is
    variable n : integer := 0;
    variable failure : boolean := false;
  begin
    assert (x\'high - x\'low + 1) <= 31
        report \"Range of sulv_to_integer argument exceeds integer range\"
        severity error;
    for i in x\'range loop
      n := n * 2;
      case x(i) is
        when \'1\' | \'H\' => n := n + 1;
        when \'0\' | \'L\' => null;
        when others =>
            -- failure := true;
            null;
      end case;
    end loop;

    assert not failure
      report \"sulv_to_integer cannot convert indefinite std_ulogic_vector\"
      severity error;
    if failure then
      return 0;
    else
      return n;
    end if;
  end slv_to_integer;

  function integer_to_slv(n, bits : integer)
      return std_logic_vector is
    variable x : std_logic_vector(bits-1 downto 0) := (others => \'0\');
    variable tempn : integer := n;
  begin
    for i in x\'reverse_range loop
      if (tempn mod 2) = 1 then
        x(i) := \'1\';
      end if;
      tempn := tempn / 2;
    end loop;

    return x;
  end integer_to_slv;
end ram_lib;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_dp2 is
    port (reset :in  std_logic;
          wr1 :in  std_logic;
          wr2 :in  std_logic;
          we1 :in  std_logic;
          we2 :in  std_logic;
          addr1 :in  std_logic_vector (7 downto 0);
          addr2 :in  std_logic_vector (7 downto 0);
          din1 :in  std_logic_vector (7 downto 0);
          din2 :in  std_logic_vector (7 downto 0);
          dout1 :out std_logic_vector (7 downto 0);
          dout2 :out std_logic_vector (7 downto 0));
end ram_dp2;


architecture arch_ram_dp2 of ram_dp2 is
   subtype word is std_logic_vector (7 downto 0);
   type ram_type is array (0 to 255) of word;  
   signal ram : ram_type ;
  
  begin
  
  write1:
    process (wr1)
    variable address1 :integer;
    begin  
    if wr1\'event and wr1=\'1\' then
      if we1=\'1\' then
        address1 := slv_to_integer (addr1);
        ram(address1) <= din1 after 2 ns;
      end if;
    end if;
   end process;

  writer2:
  process (wr2)
   variable address2 :integer;
   begin  
   if wr2\'event and wr2=\'1\' then
     if we2=\'1\' then
        address2 := slv_to_integer (addr2);
        ram(address2) <= din2 after 2 ns;
      end if;
    end if;
  end process;

  -- Handle the read ports
  read1:
  process (reset, wr1)
  begin
    if reset=\'1\' then
      dout1 <= (others=>\'0\');
    elsif wr1\'event and wr1=\'1\' then
      dout1 <= ram(slv_to_integer(addr1));
    end if;
  end process;          

read2:
process (reset, wr2)
  begin
   if reset=\'1\' then
      dout2 <= (others=>\'0\');
    elsif wr2\'event and wr2=\'1\' then
      dout2 <= ram(slv_to_integer(addr2));
    end if;
  end process;          
end arch_ram_dp2;


----------------------------------------------------------------------------
----------------------------------------------------------------------------

你的冲突仲裁机制在哪里, DPRAM不是象你描述的那样.

仲裁机制怎样来写呢  请大侠指教一下

dpram是不能同时写的, 你需要根据两面的信号判断哪一面有权力写,然后给出ready信号,另一面则给出BUSY信号, 见到READY信号的一