在MAXPLUS里面的问题 帮忙看看

我写的程序如下，在MODELSIM里面仿真没问题 经过synplify综合后的EDF文件 调入MAXPLUS里面生成SYMBOL文件然后画输入输出端口，想写输入信号波形图 但是在NODE里面没有输入信号可以加入 不知道为什么  请大侠指点
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

package ram_lib is  
  component ram16
    port (reset :in  std_logic;
          dsp_init: out std_logic ;
          wr1 :in  std_logic;
          wr2 :in  std_logic;
          we1 :in  std_logic;
          we2 :in  std_logic;
          rd1 :in std_logic;
          rd2 :in std_logic;
          addr1 :in  std_logic_vector (1 downto 0);
          addr2 :in  std_logic_vector (1 downto 0);
          din1 :in  std_logic_vector (15 downto 0);
          din2 :in  std_logic_vector (15 downto 0);
          dout1 :out std_logic_vector (15 downto 0);
          dout2 :out std_logic_vector (15 downto 0));
  end component;
  function slv_to_integer(x : std_logic_vector)
       return integer;
  function integer_to_slv(n, bits : integer)
      return std_logic_vector;  
end ram_lib;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

package body ram_lib is
  function slv_to_integer(x : std_logic_vector)
       return integer is
    variable n : integer := 0;
    variable failure : boolean := false;
  begin
    assert (x\'high - x\'low + 1) <= 31
        report \"Range of sulv_to_integer argument exceeds integer range\"
        severity error;
    for i in x\'range loop
      n := n * 2;
      case x(i) is
        when \'1\' | \'H\' => n := n + 1;
        when \'0\' | \'L\' => null;
        when others =>
            -- failure := true;
            null;
      end case;
    end loop;

    assert not failure
      report \"sulv_to_integer cannot convert indefinite std_ulogic_vector\"
      severity error;
    if failure then
      return 0;
    else
      return n;
    end if;
  end slv_to_integer;

  function integer_to_slv(n, bits : integer)
      return std_logic_vector is
    variable x : std_logic_vector(bits-1 downto 0) := (others => \'0\');
    variable tempn : integer := n;
  begin
    for i in x\'reverse_range loop
      if (tempn mod 2) = 1 then
        x(i) := \'1\';
      end if;
      tempn := tempn / 2;
    end loop;

    return x;
  end integer_to_slv;
end ram_lib;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram16 is
    port (reset :in  std_logic;
          dsp_init: out std_logic ;
          wr1 :in  std_logic;
          wr2 :in  std_logic;
          we1 :in  std_logic;
          we2 :in  std_logic;
          rd1 :in std_logic;
          rd2 :in std_logic;
          addr1 :in  std_logic_vector (1 downto 0);
          addr2 :in  std_logic_vector (1 downto 0);
          din1 :in  std_logic_vector (15 downto 0);
          din2 :in  std_logic_vector (15 downto 0);
          dout1 :out std_logic_vector (15 downto 0);
          dout2 :out std_logic_vector (15 downto 0));
end ram16;


architecture arch_ram of ram16 is
   subtype word is std_logic_vector (15 downto 0);
   type ram_type is array (0 to 3) of word;  
   signal ram : ram_type ;      
  begin        
  write1:        
  process (reset,wr1,wr2)
    variable address1 :integer;
    begin
    if reset = \'1\' and reset\'event then
    for i in 0 to 3 loop
    ram(i) <= \"0000000000000000\";    
    end loop;
    elsif wr1\'event and wr1=\'0\' then
      if we1=\'1\' then
        address1 := slv_to_integer (addr1);
        ram(address1) <= din1;        
      end if;
    elsif wr2\'event and wr2=\'0\' then
     if we2=\'1\' then
       address1 := slv_to_integer (addr2);
        ram(address1) <= din2;
      end if;
      end if;
   end process;

  read1:
  process (reset,rd1,rd2)
  variable dsp : std_logic;
  begin
    if reset = \'1\' then      
      dout1 <= (others=>\'0\');
      dout2 <= (others=>\'0\');
    elsif rd1\'event and rd1=\'0\' then
    if we1 = \'0\' then
      dout1 <= ram(slv_to_integer(addr1));      
    end if;
    elsif rd2\'event and rd2=\'0\' then
    if we2 =\'0\' then    
      dout2 <= ram(slv_to_integer(addr2));
    end if;
    end if;
  end process;          
          
end arch_ram;


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