verilog 语法

module c3(carry,clk);
   output carry;
   input clk;
   reg [3:0] counter4;
   reg  carry;
   initial counter4=0;
   always   @(negedge clk)  begin
      carry=1;
      if (counter4 == 4'b0011)
          counter4<=0;
           carry<=0;
       else    
            carry<=1;
          counter4<=counter4+1;
   end        
endmodule


以上程序为什么不能通过编译，那里有错误，请各位指教，谢谢！用它实现计数器，输出carry脉冲。

module new1(carry,clk);
output carry;
input clk;
reg [3:0] counter4;
reg carry;
initial counter4=0;
always @(negedge clk)
begin
carry=1;
if (counter4 == 4'b0011)
begin
counter4<=0;
carry<=0;
end
else
carry<=1;
counter4<=counter4+1;
end
endmodule

应该可以通过编译

module c3(carry,clk);
    output carry;
    input clk;

reg [3:0] counter4;
reg carry;

initial counter4=0;
always @(negedge clk)
begin
carry<=1;
if (counter4 == 4'b0011)
begin
counter4<=0;
  carry<=0;
           end
else
begin
carry<=1;
counter4<=counter4+1;
end
end

endmodule :)

initial counter4=0;
这类语句是不可综合的

谢谢各位指教