cy7c68013的e618（EP2/Slave FIFO Configuration）寄存器各位的功能是什么？

下载的fx2说明书里只有寄存器地址，以及每一位的名称，却没有说明各个位在0或者1时分别都是什么作用，谁能加以指点？如果谁有寄存器的详细说明还望告知，不胜感激。

怎么可能？在整个文档里搜！手头上没资料，晚上查到给你贴出来
不过建议你自己搜一下。

我用google搜过，但是好多都是跟我手头上的是一样的，没有具体说明。

你说的e608是UART的设置寄存器，说明如下：
Table 14-9. UART230 Register ― Address 0xE608
Bit Function
UART230.7:2 Reserved
UART230.1 230UART1 - Enable high-speed baud rate generator for serial port 1. When 230UART1
= 1, a 115.2K baud (if SMOD1 = 0) or 230.4K baud (if SMOD1 = 1) clock is provided to
serial port 1. When 230UART1 = 0, serial port 1’s baud clock is provided by one of the
sources shown in Tabl e14-7.
UART230.0 230UART0 - Enable high-speed baud rate generator for serial port 0. When 230UART0
= 1, a 115.2K baud (if SMOD0 = 0) or 230.4K baud (if SMOD0 = 1) clock is provided to
serial port 0. When 230UART1 = 0, serial port 0’s baud clock is provided by one of the
sources shown in Tabl e14-7.

EP2FIFOCFG的地址是E618说明如下：
bit7 0
Bit 6 INFM1 IN Full Minus One
When a FIFO configuration register’s ‘INEARLY’ or INFM bit is set to 1, the FIFO flags for that
endpoint become valid one sample earlier than when the FULL condition occurs. These bits
take effect only when the FIFOS are operating synchronously―according to an internally- or
externally-supplied clock. Having the FIFO flag indications a clock early simplifies some synchronous
interfaces (applies only to IN endpoints).

Bit 5 OEP1 OUT Empty Plus One
When a FIFO configuration register’s ‘OUTEARLY’ or OEP1 bit is set to 1, the FIFO flags for
that endpoint become valid one sample earlier than when the EMPTY condition occurs. These
bits take effect only when the FIFOS are operating synchronously―according to an internally-
or externally-supplied clock. Having the FIFO flag indications a clock early simplifies some
synchronous interfaces (applies only to OUT endpoints).

Bit 4 AUTOOUT Instantaneous Connection to Endpoint FIFO
  This bit applies only to OUT endpoints.
When AUTOOUT=1, as soon as a buffer fills with USB data, the buffer is automatically and
instantaneously committed to the endpoint FIFO bypassing the CPU. The endpoint FIFO flags
and buffer counts immediately indicate the change in FIFO status. Refer to the description of
the DYN_OUT bit in Section 15.5.9.
  When AUTOOUT=0, as soon as a buffer fills with USB data, an endpoint interrupt is asserted.
The connection of the buffer to the endpoint FIFO is under control of the firmware, rather than
automatically being connected. Using this method, the firmware can inspect the data in OUT
packets, and based on what it finds, choose to include that packet in the endpoint FIFO or not.
The firmware can even modify the packet data, and then commit it to the endpoint FIFO. Refer
to Enhanced Packet Handling in Section 15.5.9.
The SKIP bit (in the EPxBCL registers) chooses between skipping and committing packet
data. Refer to OUTPKTEND in Section 15.6.8.

Bit 3 AUTOIN Auto Commit to SIE
This bit applies only to IN endpoints.
FX2 has EPxAUTOINLEN registers that allow the firmware to configure endpoints to sizes
smaller than the physical memory sizes used to implement the endpoint buffers (512 or 1024
bytes). For example, suppose the firmware configures the EP2 buffer to be 1024 bytes, and
then sets up EP2 as a 760-byte endpoint by setting EP2AUTOINLEN=760 (this must match
the wMaxPacketSize value in the endpoint descriptor). This makes EP2 appear to be a 760-
byte endpoint to the USB host, even though EP2’s physical buffer is 1024 bytes.
When AUTOIN=1, FX2 automatically packetizes and dispatches IN packets according to the
packet length value it finds in the EPxAUTOINLEN registers. In this example, the GPIF (or an
external master, if the FX2 is in Slave FIFO mode) could load the EP2 buffer with 950 bytes,
which the FX2 logic would then automatically send as two packets, of 760 and 190 bytes.
Refer to Enhanced Packet Handling in Section 15.5.9.
When AUTOIN=0, each packet has to initially be manually committed to SIE, (prime the
pump). See Section 15.5.9, "Chip Revision Control".

Bit 2 ZEROLENIN Enable Zero-length IN Packets
When this flag is '1', a zero length packet will be sent when PKTEND is activated and there are
no bytes in the current packet. If this flag is '0', zero length packets will not be sent on
PKTEND.

Bit 0 WORDWIDE Select Byte/Word FIFOs on PORTB/D Pins
This bit selects byte or word FIFOS on the PORTB and PORTD pins. The WORD bit applies
“for IFCFG=11 or 10”.
The OR of all 4 WORDWIDE bits is what causes PORTD to be PORTD or FD[15:8]. The individual
WORDWIDE bits indicate how data will be passed for each individual endpoint.

到www.cypress.com下载一个EZ-USB FX2 ManualTechnical Reference
就在芯片说明的地方，这些东西就是从里面摘出来的。

技术参考下在地址：直接放在flashget或者netant里下载
http://www.cypress.com/cfuploads/support/developer_kits/EZ-USB_FX2_TRM_version2-2.pdf
    软件包下在地址：同上
http://www.cypress.com/cfuploads/support/developer_kits/EZ-USB_devtools_version_261700.zip
软件包下在完成之后安装，可以在安装目录下找到demo板设计的硬件资源，软件源代码以及相应文档！
如果你没有装那些下载软件，就到下面页面下载。
http://www.cypress.com/support/dev_kit.cfm?objectID=140FF03F-DFF5-44BE-8215814F6FEB75CC&tid=EF028E39-2658-41C0-828715F47620AEE8

Cypress的手册上对于AUTOOUT=1的初始化代码是有问题的，请参照Cypress提供的Example，你会发现这样的Note：

需要根据Cypress提供的流程来处理，否则会出现问题的。
  //  (2)...when REVCTL.1=1, core blocks auto arming of OUT endp's
  //      ...see above EPxBCL/OUTPKTEND sequence(s)
  //      ...sequence is as follows:
  //      ...(a) REVCTL.1=1
  //      ...(b) FIFORESET (as above)
  //      ...(c) EPxBCL/OUTPKTEND (as above)
  //      ...(d) AUTOOUT=1