68013同步传输设计

有哪位兄弟做过同步传输的说一声，非常感谢！！我现在的配置和CPLD时序有问题请教

什么问题?

void TD_Init(void)             // Called once at startup
{
   // set the CPU clock to 48MHz
  // CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
   SYNCDELAY;  
   CPUCS=0x10;  //set to 48MHz mode
   SYNCDELAY;
   REVCTL= 0x03; // must set revctl.0 and revctl.1 to 1
   // set the slave FIFO interface to 48MHz
   SYNCDELAY;
   IFCONFIG = 0x43; //EDIT HERE//change to synchronously and outsource clock.
   //0100 0011  0x43 means out source, synch mode
   //1110 0011  0xE3 means internal source 48Mhz ifclk out put, synch mode
   //1100 1011
   //bit 7 0 out ifclk source 1 internal clk source
   //bit 6  0 30Mhz  1 48Mhz
   //bit 5 ifclkOE  0 tir-state 1 drive
   //bit 4 ifCLKPOL  ifclk inverted 0 normal 1 inverted
   //bit 3 Async 0 synch  1 async
   //bit 2 GSTATE  not use set to 0
   //bit 1  1   slave fifo
   //bit 0  1
  //reset the fifo
  SYNCDELAY;
  EP2CFG=0xA2;  //10 10  0 0 10

  //bit 7 valid
  //bit 6 out 0 in 1
  //bit 5,4 10  bulk
  //bit 3 0 512
  //bit 2 must set to 0
  //bit 1,0  10 double buffer
  SYNCDELAY;
  EP4CFG=0xA2;
  SYNCDELAY;
  EP6CFG=0xe2;//11100010
  SYNCDELAY;
  EP8CFG=0xe2;//11100010// xxxxxx10 double buffer

  SYNCDELAY;
  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x02;             // reset, FIFO 2
  SYNCDELAY;                    //
  FIFORESET = 0x04;             // reset, FIFO 4
  SYNCDELAY;                    //
  FIFORESET = 0x06;             // reset, FIFO 6
  SYNCDELAY;                    //
  FIFORESET = 0x08;             // reset, FIFO 8
  SYNCDELAY;                    //
  FIFORESET = 0x00;             // deactivate NAK-ALL
  
  //set the flag port
  SYNCDELAY;
  PINFLAGSAB = 0x98;            // FLAGA - fixed EP2EF, FLAGB - fixed EP4EF
  SYNCDELAY;
  PINFLAGSCD = 0xFE;            // FLAGC - fixed EP6FF, FLAGD - fixed EP8FF
  SYNCDELAY;
  PORTACFG |= 0x80;              // FLAGD, set alt. func. of PA7 pin
  SYNCDELAY;
  FIFOPINPOLAR = 0x00;          // all signals active low
  //
  
  //set each endpoint
  // handle the case where we were already in AUTO mode...
  SYNCDELAY;
  EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=0

  SYNCDELAY;
  EP2FIFOCFG = 0x10;            // AUTOOUT=1, WORDWIDE=0 0 means 8bits,1 means 16bits

  
  // handle the case where we were already in AUTO mode...
  SYNCDELAY;
  EP4FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=0

  SYNCDELAY;
  EP4FIFOCFG = 0x10;            // AUTOOUT=1, WORDWIDE=1   enable 16bit mode

  SYNCDELAY;
  EP6FIFOCFG = 0x0c;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0  8 bit mode 1 16 bit mode
  SYNCDELAY;
  EP8FIFOCFG = 0x0c;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0  8 bit mode
  SYNCDELAY;
  EP6AUTOINLENH = 0x02; // Auto-commit 512-byte packets
  SYNCDELAY;
  EP6AUTOINLENL = 0x00;
  SYNCDELAY;
  EP8AUTOINLENH = 0x02; // Auto-commit 512-byte packets
  SYNCDELAY;
  EP8AUTOINLENL = 0x00;

  
  // out endpoints do not come up armed
 
  SYNCDELAY;
  OUTPKTEND=0x82;
  SYNCDELAY;
  OUTPKTEND=0x82;

  
  
 // SYNCDELAY;
 // EP4BCL = 0x80;                // arm EP4OUT by writing byte count w/skip.
 // SYNCDELAY;                    
 // EP4BCL = 0x80;  
 // SYNCDELAY;
 // EP4FIFOCFG = 0x10;            // AUTOOUT=1, WORDWIDE=1   enable 16bit mode
  SYNCDELAY;
  OUTPKTEND=0x84;
  SYNCDELAY;
  OUTPKTEND=0x84;
  SYNCDELAY;

  
}
上面是我用SLAVE FIFO 同步读的固件配置,TD_POLL没有做任何事情,你觉得这样的配置有问题吗?我遇到的问题是,程序下载到EEPROM中,然后从主机读出相关寄存器值,发现有的值和程序不一样,特别是EPXFIFOCFG的值,我怀疑是我硬件板有问题了.但是异步的配置下去是正确的,有点不明白是什么问题.而且同步的配置,在后来更新的一块硬件板上,出现的问题没有前面一块严重,但是 EPXFIFOCFG 个别还是有问题.比如前面一个EPXFIFOCFG大多会出现05值,而正确的是EP2FIFOCFG=10,EP4FIFOCFG=10,EP6FIFOCFG=0C,EP8FIFOCFG=0C.在新板上会出现EP4FIFOCFG=00.请问是什么问题呢?

Cypress的手册上对于AUTOOUT=1的初始化代码是有问题的，请参照Cypress提供的Example，你会发现这样的Note：

需要根据Cypress提供的流程来处理，否则会出现问题的。
  //  (2)...when REVCTL.1=1, core blocks auto arming of OUT endp's
  //      ...see above EPxBCL/OUTPKTEND sequence(s)
  //      ...sequence is as follows:
  //      ...(a) REVCTL.1=1
  //      ...(b) FIFORESET (as above)
  //      ...(c) EPxBCL/OUTPKTEND (as above)
  //      ...(d) AUTOOUT=1