为什么都只有问题,没有答案????---68013写不成功

  我想要用68013的slave FIFO跟FPGA通信,EP2 Auto-out,EP6 Auto-in,异步模式,现在能够Auto-in了,但是每次用WinDriver往EP2写数据的时候都不成功,不管FPGA有没有程序都提示超时
如果是因为外部没有读数据的原因至少应该能够写进去1024B啊

我在这个论坛上也看到很多提出过一样问题的帖子,可惜最后楼主都是一句"问题解决了"就完了,也没说是怎么解决的

下面的是我的固件,麻烦各位大虾帮忙看看,谢谢了~~~


void TD_Init(void)             // Called once at startup
{
    // set the CPU clock to 48MHz
    CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

       REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
    SYNCDELAY;                  

    EP1OUTCFG = 0xA0;
    EP1INCFG = 0xA0;
    SYNCDELAY;  
  
  
  
    EP2CFG    = 0XAA;           //EP2: out,1024,2*buffer
    SYNCDELAY;
    EP4CFG    = 0X00;           //EP4: invalid
    SYNCDELAY;
    EP6CFG    = 0XEA;           //EP6: in ,1024,2*buffer
    SYNCDELAY;
    EP8CFG    = 0X00;           //EP8: invalid
    SYNCDELAY;
  
  
    

    // since the defaults are double buffered we must write dummy byte counts twice
    EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
    SYNCDELAY;                    //                   //
    EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
    SYNCDELAY;                    //

    FIFORESET = 0X80; //Reset all FIFOs;
    SYNCDELAY;
    FIFORESET = 0X02;
    SYNCDELAY;
    FIFORESET = 0X04;
    SYNCDELAY;
    FIFORESET = 0X06;
    SYNCDELAY;
    FIFORESET = 0X08;
    SYNCDELAY;
    FIFORESET = 0X00;
    SYNCDELAY;

    IFCONFIG = 0xCB;   // this defines the external interface to be the following:
                     // use IFCLK pin driven by internal logic, clk frequency is 48MHz
                     // use slave FIFO interface pins driven async by external master
    SYNCDELAY;

    EP6AUTOINLENH=0X04;         //EP6 auto in length: 1024
    SYNCDELAY;
    EP6AUTOINLENL=0X00;
    SYNCDELAY;


    EP2FIFOCFG= 0X10;           //EP2:Auto out
    SYNCDELAY;
    EP6FIFOCFG= 0X08;           //EP6:Auto in
    SYNCDELAY;

    

//-----------------------------------------------------------------------------

    PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
                     // FLAGB as full flag, as pointed to by FIFOADR[1:0]
    SYNCDELAY;

    PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
    SYNCDELAY;

    PORTACFG = 0x00;   // used PA7/FLAGD  a PORTA pin  ,no as a FIFO flag SLCS
    SYNCDELAY;

    FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
    SYNCDELAY;
  

}

大侠们,救命啊~~~~~

问题已经解决!!!-----不能破了前辈们的规矩~~~

interesting...