68013的FIFO Slave 调不通。请各位会诊

68013的FIFO Slave 调不通。

void TD_Init(void)             // Called once at startup
{
   // set the CPU clock to 48MHz
   CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY;
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x04;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x08;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY; // this defines the external interface to be the following:
IFCONFIG = 0x43; // use IFCLK pin driven by external logic (5MHz to 48MHz)
// use slave FIFO interface pins driven sync by external master
EP8FIFOCFG = 0x0C; // this lets the FX2 auto commit IN packets, gives the
// ability to send zero length packets,
// and sets the slave FIFO data interface to 8-bits
EP8CFG = 0xE0; // sets EP8 valid for IN's
// and defines the endpoint for 512 byte packets, 2x buffered
PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY; // FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
// won't generally need FLAGD
PORTACFG |= 0x40;
//PORTACFG = 0x00; // used PA7/FLAGD as a port pin, not as a FIFO flag
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
SYNCDELAY;
EP8AUTOINLENH = 0x02; // you can define these as you wish,
SYNCDELAY; // to have the FX2 automatically limit IN's
EP8AUTOINLENL = 0x00;
SYNCDELAY;
EP8FIFOPFH = 0x82; // you can define the programmable flag (FLAGA)
SYNCDELAY; // to be active at the level you wish
EP8FIFOPFL = 0x00;
SYNCDELAY; // out endpoints do not POR (power-on reset) armed
EP2BCL = 0x80; // since the defaults are double buffered we must
SYNCDELAY; // write dummy byte counts twice
EP2BCL = 0x80; // arm EP2OUT & EP4OUT by writing to the byte count w/skip.
SYNCDELAY;
EP4BCL = 0x80;
SYNCDELAY;
EP4BCL = 0x80;
}
别的程序是原始例子，一点没改。
外逻辑用的是一个51单片机，程序如下：
#include <reg51.h>                //头文件
#include <stdio.h>

sbit SLRD=P1^4;                       //定义控制引脚
sbit SLWR=P1^5;
sbit SLCS=P1^3;
sbit SLOE=P1^1;
sbit FIFOADR1=P1^2;
sbit FIFOADR0=P1^0;
sbit Start=P3^7;

void main()                        //主程序
{
    int FD;
    int i;

    FIFOADR0=1;                    //选择EP8
    FIFOADR1=1;
    SLWR=0;                        //初始化各个控制引脚
    SLRD=1;
    SLCS=0;
    SLOE=0;
    P2=0x55;

    while(1)                       //主循环
    {
            for (i=0;i<512;i++)
            {
                SLWR=0;
                 P2=0x55;           //循环写入512个数据0x05
                SLWR=1;
            }
    }
}

用的是TRM上的9.3.10,用的是异步的方式。

现象：用CyConsole进行bulk传输时（EP8 IN） 显示传输失败。单片机上的IFCLK引脚显示是高电平,是不是说明没有波形，是不是应该有方波.