我按照书上的编的程序，综合都通过了，但是MAP时提示出错，请问是什么原因：

下面是提示信息：
$ Start of Compile
#Wed Jan 22 19:49:37 2003

Synplicity Verilog Compiler, version 7.0.0, Build 130R, built Nov 16 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved

@I::\"D:\\Project\\RISC_CPU\\statectl.v\"
@I::\"D:\\Project\\RISC_CPU\\addrmux.v\"
@I::\"D:\\Project\\RISC_CPU\\alu.v\"
@I::\"D:\\Project\\RISC_CPU\\clkgenerator.v\"
@I::\"D:\\Project\\RISC_CPU\\cpu.v\"
@I::\"D:\\Project\\RISC_CPU\\datactl.v\"
@I::\"D:\\Project\\RISC_CPU\\diliver_op_ir.v\"
@I::\"D:\\Project\\RISC_CPU\\inregister.v\"
@I::\"D:\\Project\\RISC_CPU\\procounter.v\"
@I::\"D:\\Project\\RISC_CPU\\accum.v\"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module cpu
Synthesizing module clkgenerator
@W:\"D:\\Project\\RISC_CPU\\clkgenerator.v\":66:0:66:6|Ignoring initial statement
Synthesizing module accum
Synthesizing module alu
Synthesizing module statectl
@N:\"D:\\Project\\RISC_CPU\\statectl.v\":84:0:84:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@W:\"D:\\Project\\RISC_CPU\\statectl.v\":62:7:62:14|Input Int_flag is unused
Synthesizing module addrmux
Synthesizing module datactl
Synthesizing module diliver_op_ir
Synthesizing module inregister
Synthesizing module procounter
Synthesizing module cpu
@W:\"D:\\Project\\RISC_CPU\\cpu.v\":23:9:23:18|*Input Int_flag to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@END
Process took 0.12 seconds realtime, 0.12 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.0.0, Build 129R, built Nov 12 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved
Automatic dissolve at startup in view:work.cpu(verilog) of p_conut(procounter)
Automatic dissolve at startup in view:work.cpu(verilog) of op_ir(diliver_op_ir)
Automatic dissolve at startup in view:work.cpu(verilog) of data_controller(datactl)
Automatic dissolve at startup in view:work.cpu(verilog) of addr_mux(addrmux)
Automatic dissolve at startup in view:work.cpu(verilog) of acc(accum)
Automatic dissolve at startup in view:work.cpu(verilog) of clk_gen(clkgenerator)
@N:\"d:\\project\\risc_cpu\\procounter.v\":69:0:69:5|Found counter in view:work.cpu(verilog) inst p_conut.Pc_addr[12:0]
Encoding state machine work.statectl(verilog)-state_h.state[7:0]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
Automatic dissolve during optimization of view:work.cpu(verilog) of instr_reg(inregister)

Clock Buffers:
  Inserting Clock buffer for port Clk, TNM=Clk

Net work.cpu(verilog)-Data_c[0] has mixed driver types
  output pin:O inst:Data_ibuf[0] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[0] of PrimLib.tri(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[0] of PrimLib.xor(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_0 of PrimLib.xor(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[0] of PrimLib.mux(prim)
  input  pin:I[1] inst:alu1.Alu_out_5[0] of PrimLib.and(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_0.G_41 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_8.G_33 of PrimLib.obs(prim)
Net work.cpu(verilog)-Data_c[1] has mixed driver types
  output pin:O inst:Data_ibuf[1] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[1] of PrimLib.tri(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[1] of PrimLib.xor(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_1 of PrimLib.xor(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[1] of PrimLib.mux(prim)
  input  pin:I[1] inst:alu1.Alu_out_5[1] of PrimLib.and(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_1.G_42 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_9.G_34 of PrimLib.obs(prim)
Net work.cpu(verilog)-Data_c[2] has mixed driver types
  output pin:O inst:Data_ibuf[2] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[2] of PrimLib.tri(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[2] of PrimLib.xor(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_2 of PrimLib.xor(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[2] of PrimLib.mux(prim)
  input  pin:I[1] inst:alu1.Alu_out_5[2] of PrimLib.and(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_2.G_43 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_10.G_35 of PrimLib.obs(prim)
Net work.cpu(verilog)-Data_c[3] has mixed driver types
  output pin:O inst:Data_ibuf[3] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[3] of PrimLib.tri(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[3] of PrimLib.xor(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_3 of PrimLib.xor(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[3] of PrimLib.mux(prim)
  input  pin:I[1] inst:alu1.Alu_out_5[3] of PrimLib.and(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_3.G_44 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_11.G_36 of PrimLib.obs(prim)
Net work.cpu(verilog)-Data_c[4] has mixed driver types
  output pin:O inst:Data_ibuf[4] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[4] of PrimLib.tri(prim)
  input  pin:I[0] inst:alu1.Alu_out_5[4] of PrimLib.and(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[4] of PrimLib.mux(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_4 of PrimLib.xor(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[4] of PrimLib.xor(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_4.G_45 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_12.G_37 of PrimLib.obs(prim)
Net work.cpu(verilog)-Data_c[5] has mixed driver types
  output pin:O inst:Data_ibuf[5] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[5] of PrimLib.tri(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_13.G_38 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_5.G_46 of PrimLib.obs(prim)
  input  pin:I[0] inst:alu1.Alu_out_5[5] of PrimLib.and(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[5] of PrimLib.mux(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_5 of PrimLib.xor(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[5] of PrimLib.xor(prim)
Net work.cpu(verilog)-Data_c[6] has mixed driver types
  output pin:O inst:Data_ibuf[6] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[6] of PrimLib.tri(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_14.G_39 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_6.G_47 of PrimLib.obs(prim)
  input  pin:I[0] inst:alu1.Alu_out_5[6] of PrimLib.and(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[6] of PrimLib.mux(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_6 of PrimLib.xor(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[6] of PrimLib.xor(prim)
Net work.cpu(verilog)-Data_c[7] has mixed driver types
  output pin:O inst:Data_ibuf[7] of VIRTEX.IBUF(PRIM)
  output pin:OUT[0] inst:data_controller.Data_1[7] of PrimLib.tri(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_15.G_40 of PrimLib.obs(prim)
  input  pin:IN inst:instr_reg.Opc_iraddr_7.G_48 of PrimLib.obs(prim)
  input  pin:I[0] inst:alu1.Alu_out_5[7] of PrimLib.and(prim)
  input  pin:B[0] inst:alu1.Alu_out_12_1[7] of PrimLib.mux(prim)
  input  pin:I[0] inst:alu1.un2_Alu_out_axb_7 of PrimLib.xor(prim)
  input  pin:I[1] inst:alu1.Alu_out_6[7] of PrimLib.xor(prim)
primopt.c:409 Error: Aborting because of driver errors
Process took 2.985 seconds realtime, 2.984 seconds cputime

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