阅读:3758回复:4
多谢光顾。使用gpif者请进,对固件精通者也可
各位看看下面这段程序实现什么功能 啊?为什么固件里面加了这个in_enable判断读出来的结果明显不一样啊
case VX_B3: // enable IN transfers { in_enable = TRUE; *EP0BUF = VX_B3; EP0BCH = 0; EP0BCL = 1; EP0CS |= bmHSNAK; break; } 我主要想让大家帮我看看这段程序是如何执行的 |
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沙发#
发布于:2003-11-11 16:41
你给的信息太少了吧。看都看不明白。
好象是端点0的读写吧。 把VX_B3放到端点0的buffer里面去? 那是in还是out呢?应该是in。 这样in_enable 就有用了。 EP0BCH = 0; EP0BCL = 1; // 这2个做什么? EP0CS |= bmHSNAK; // 这是选择? ================== 我不清楚,瞎猜的。 等高手来了解释吧。 |
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板凳#
发布于:2003-11-11 17:14
谢谢
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地板#
发布于:2003-11-11 17:49
附上程序
#pragma NOIV // Do not generate interrupt vectors //----------------------------------------------------------------------------- // File: FX2_to_extsyncFIFO.c // Contents: Hooks required to implement FX2 GPIF to external sync. FIFO // interface using CY4265-15AC // // Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved //----------------------------------------------------------------------------- #include \"fx2.h\" #include \"fx2regs.h\" #include \"fx2sdly.h\" // SYNCDELAY macro, see Section 15.14 of FX2 Tech. // Ref. Manual for usage details. //#define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1 #define EXTFIFONOTEMPTY GPIFREADYSTAT & 0x3e #define GPIFTRIGRD 4 #define GPIF_EP2 0 #define GPIF_EP4 1 #define GPIF_EP6 2 #define GPIF_EP8 3 extern BOOL GotSUD; // Received setup data flag extern BOOL Sleep; extern BOOL Rwuen; extern BOOL Selfpwr; BYTE Configuration; // Current configuration BYTE AlternateSetting; // Alternate settings BOOL in_enable = FALSE; // flag to enable IN transfers BOOL enum_high_speed = FALSE; // flag to let know FX2 enumerated at high speed extern const char xdata FlowStates[36]; //----------------------------------------------------------------------------- // Task Dispatcher hooks // The following hooks are called by the task dispatcher. //----------------------------------------------------------------------------- void Setup_FLOWSTATE_Write ( void ); void Setup_FLOWSTATE_Read ( void ); void GpifInit (); void TD_Init(void) // Called once at startup { // set the CPU clock to 48MHz CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); SYNCDELAY; EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered SYNCDELAY; EP4CFG = 0x00; // EP4 not valid SYNCDELAY; EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered SYNCDELAY; EP8CFG = 0x00; // EP8 not valid SYNCDELAY; FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host SYNCDELAY; FIFORESET = 0x02; // reset EP2 FIFO SYNCDELAY; FIFORESET = 0x06; // reset EP6 FIFO SYNCDELAY; FIFORESET = 0x00; // clear NAKALL bit to resume normal operation SYNCDELAY; EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit SYNCDELAY; EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops SYNCDELAY; EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops SYNCDELAY; GpifInit (); // initialize GPIF registers SYNCDELAY; EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag SYNCDELAY; EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag SYNCDELAY; // global flowstate register initializations FLOWLOGIC = FlowStates[19]; // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 (FIFO Flag) SYNCDELAY; FLOWSTB = FlowStates[22]; // 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe SYNCDELAY; GPIFHOLDAMOUNT = FlowStates[26]; // hold data for one half clock (10ns) assuming 48MHz IFCLK SYNCDELAY; FLOWSTBEDGE = FlowStates[24]; // move data on both edges of clock SYNCDELAY; FLOWSTBHPERIOD = FlowStates[25]; // 20.83ns half period SYNCDELAY; } void TD_Poll(void) { if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE { if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there\'s a packet in the peripheral domain for EP2 { if(enum_high_speed) { SYNCDELAY; GPIFTCB1 = 0x00; // setup transaction count (512 bytes/2 for word wide -> 0x0100) SYNCDELAY; GPIFTCB0 = 0x20; SYNCDELAY; } else { SYNCDELAY; GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20) SYNCDELAY; GPIFTCB0 = 0x20; SYNCDELAY; } Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation SYNCDELAY; GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO SYNCDELAY; while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit { ; } SYNCDELAY; } } if(in_enable) { if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE { if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty { if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full { if(enum_high_speed) { SYNCDELAY; GPIFTCB1 = 0x04; // setup transaction count (512 bytes/2 for word wide -> 0x0100) SYNCDELAY; GPIFTCB0 = 0x00; SYNCDELAY; } else { SYNCDELAY; GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20) SYNCDELAY; GPIFTCB0 = 0x20; SYNCDELAY; } Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation SYNCDELAY; GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO SYNCDELAY; while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit { ; } SYNCDELAY; } } } } } BOOL TD_Suspend(void) // Called before the device goes into suspend mode { return(TRUE); } BOOL TD_Resume(void) // Called after the device resumes { return(TRUE); } //----------------------------------------------------------------------------- // Device Request hooks // The following hooks are called by the end point 0 device request parser. //----------------------------------------------------------------------------- BOOL DR_GetDescriptor(void) { return(TRUE); } BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received { if( EZUSB_HIGHSPEED( ) ) { // FX2 enumerated at high speed SYNCDELAY; // EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes SYNCDELAY; // EP6AUTOINLENL = 0x00; SYNCDELAY; enum_high_speed = TRUE; } else { // FX2 enumerated at full speed SYNCDELAY; EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes SYNCDELAY; EP6AUTOINLENL = 0x40; SYNCDELAY; enum_high_speed = FALSE; } Configuration = SETUPDAT[2]; return(TRUE); // Handled by user code } BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received { EP0BUF[0] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_SetInterface(void) // Called when a Set Interface command is received { AlternateSetting = SETUPDAT[2]; return(TRUE); // Handled by user code } BOOL DR_GetInterface(void) // Called when a Set Interface command is received { EP0BUF[0] = AlternateSetting; EP0BCH = 0; EP0BCL = 1; return(TRUE); // Handled by user code } BOOL DR_GetStatus(void) { return(TRUE); } BOOL DR_ClearFeature(void) { return(TRUE); } BOOL DR_SetFeature(void) { return(TRUE); } #define VX_B2 0xB2 // reset the external FIFO #define VX_B3 0xB3 // enable IN transfers #define VX_B4 0xB4 // disable IN transfers #define VX_B5 0xB5 // read GPIFREADYSTAT register #define VX_B6 0xB6 // read GPIFTRIG register BOOL DR_VendorCmnd(void) { switch (SETUPDAT[1]) { case VX_B2: { // reset the external FIFO OEB |= 0xFF; // turn on PA2 as output pin IOB |= 0x80; // pull PA2 high initially IOB &= 0x80; // bring PA2 low EZUSB_Delay (100); // keep PA2 low for ~1ms, more than enough time IOB |= 0x80; //OEA |= 0x04; // turn on PA2 as output pin //IOA |= 0x04; // pull PA2 high initially //IOA &= 0xFB; // bring PA2 low //EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time //IOA |= 0x04; // bring PA2 high *EP0BUF = VX_B2; EP0BCH = 0; EP0BCL = 1; // Arm endpoint with # bytes to transfer EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request break; } case VX_B3: // enable IN transfers { in_enable = TRUE; *EP0BUF = VX_B3; EP0BCH = 0; EP0BCL = 1; EP0CS |= bmHSNAK; break; } case VX_B4: // disable IN transfers { OEB |= 0xFF; // turn on PA2 as output pin IOB |= 0xA0; // pull PA2 high initially IOB &= 0xA0; // bring PA2 low EZUSB_Delay (100); // keep PA2 low for ~1ms, more than enough time IOB |= 0xA0; //OEA |= 0x04; // turn on PA2 as output pin //IOA |= 0x04; // pull PA2 high initially //IOA &= 0xFB; // bring PA2 low //EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time //IOA |= 0x04; // bring PA2 high *EP0BUF = VX_B4; EP0BCH = 0; EP0BCL = 1; // Arm endpoint with # bytes to transfer EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request break; } case VX_B5: // read GPIFREADYSTAT register { EP0BUF[0] = VX_B5; SYNCDELAY; EP0BUF[1] = GPIFREADYSTAT; SYNCDELAY; EP0BCH = 0; EP0BCL = 2; EP0CS |= bmHSNAK; break; } case VX_B6: // read GPIFTRIG register { EP0BUF[0] = VX_B6; SYNCDELAY; EP0BUF[1] = GPIFTRIG; SYNCDELAY; EP0BCH = 0; EP0BCL = 2; EP0CS |= bmHSNAK; break; } default: return(TRUE); } return(FALSE); } //----------------------------------------------------------------------------- // USB Interrupt Handlers // The following functions are called by the USB interrupt jump table. //----------------------------------------------------------------------------- // Setup Data Available Interrupt Handler void ISR_Sudav(void) interrupt 0 { GotSUD = TRUE; // Set flag EZUSB_IRQ_CLEAR(); USBIRQ = bmSUDAV; // Clear SUDAV IRQ } // Setup Token Interrupt Handler void ISR_Sutok(void) interrupt 0 { EZUSB_IRQ_CLEAR(); USBIRQ = bmSUTOK; // Clear SUTOK IRQ } void ISR_Sof(void) interrupt 0 { EZUSB_IRQ_CLEAR(); USBIRQ = bmSOF; // Clear SOF IRQ } void ISR_Ures(void) interrupt 0 { // whenever we get a USB reset, we should revert to full speed mode pConfigDscr = pFullSpeedConfigDscr; ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR; pOtherConfigDscr = pHighSpeedConfigDscr; ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR; EZUSB_IRQ_CLEAR(); USBIRQ = bmURES; // Clear URES IRQ } void ISR_Susp(void) interrupt 0 { Sleep = TRUE; EZUSB_IRQ_CLEAR(); USBIRQ = bmSUSP; } void ISR_Highspeed(void) interrupt 0 { if (EZUSB_HIGHSPEED()) { pConfigDscr = pHighSpeedConfigDscr; ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR; pOtherConfigDscr = pFullSpeedConfigDscr; ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR; } EZUSB_IRQ_CLEAR(); USBIRQ = bmHSGRANT; } void ISR_Ep0ack(void) interrupt 0 { } void ISR_Stub(void) interrupt 0 { } void ISR_Ep0in(void) interrupt 0 { } void ISR_Ep0out(void) interrupt 0 { } void ISR_Ep1in(void) interrupt 0 { } void ISR_Ep1out(void) interrupt 0 { } void ISR_Ep2inout(void) interrupt 0 { } void ISR_Ep4inout(void) interrupt 0 { } void ISR_Ep6inout(void) interrupt 0 { } void ISR_Ep8inout(void) interrupt 0 { } void ISR_Ibn(void) interrupt 0 { } void ISR_Ep0pingnak(void) interrupt 0 { } void ISR_Ep1pingnak(void) interrupt 0 { } void ISR_Ep2pingnak(void) interrupt 0 { } void ISR_Ep4pingnak(void) interrupt 0 { } void ISR_Ep6pingnak(void) interrupt 0 { } void ISR_Ep8pingnak(void) interrupt 0 { } void ISR_Errorlimit(void) interrupt 0 { } void ISR_Ep2piderror(void) interrupt 0 { } void ISR_Ep4piderror(void) interrupt 0 { } void ISR_Ep6piderror(void) interrupt 0 { } void ISR_Ep8piderror(void) interrupt 0 { } void ISR_Ep2pflag(void) interrupt 0 { } void ISR_Ep4pflag(void) interrupt 0 { } void ISR_Ep6pflag(void) interrupt 0 { } void ISR_Ep8pflag(void) interrupt 0 { } void ISR_Ep2eflag(void) interrupt 0 { } void ISR_Ep4eflag(void) interrupt 0 { } void ISR_Ep6eflag(void) interrupt 0 { } void ISR_Ep8eflag(void) interrupt 0 { } void ISR_Ep2fflag(void) interrupt 0 { } void ISR_Ep4fflag(void) interrupt 0 { } void ISR_Ep6fflag(void) interrupt 0 { } void ISR_Ep8fflag(void) interrupt 0 { } void ISR_GpifComplete(void) interrupt 0 { } void ISR_GpifWaveform(void) interrupt 0 { } void Setup_FLOWSTATE_Read ( void ) { FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003 SYNCDELAY; FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows) FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow) SYNCDELAY; } void Setup_FLOWSTATE_Write ( void ) { FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001 SYNCDELAY; FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows) SYNCDELAY; FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow) SYNCDELAY; } |
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地下室#
发布于:2005-03-16 22:06
有个开发工具GPIF designer 有人熟悉吗?请教啊!
什么叫 FLOW STATE? A Master Strobe Pin? NON decision point? 有怎么设置DESIGNER的例子吗? :( |
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