这是amcc的bug码？哪位大虾可以给翻译一下，谢谢！

Personally, I wouldn\'t bother.

I worked on a 5933 design 3 years ago. Several bugs in the 5933 resulted
in the entire project being aborted.

The most serious of these is that when operating in master mode, if the
PCI target happens to request a retry on the last item of your burst
then the following events happen.

1) Your FIFO is marked empty (which it is)

2) You load the next target address (because your\'re ready to do the
next DMA and you think your FIFO is empty)

3) The 5933 uses THIS NEW ADDRESS to write the retried item which is
sitting in an undocumented \'holding\' register off the end of the FIFO -
i.e. writes the last item of data for your last DMA burst to the first
address of your new DMA.

4) The 5933 then goes and increments the target address register and
delivers the rest of your DMA data to addr+4 etc.

It is not possible to work around this bug without snooping the PCI bus
(and consequently breaking the loading rules) to determine that retry
has happened at the end of your DMA.  I have not seen this bug either
acknowledged by AMCC or reported fixed. I\'d also be happy to see AMCC
say that this bug has been found and fixed, but unless it has, your
design will be doomed so far as DMA mastering is concerned.


Sent via Deja.com http://www.deja.com/
Before you buy.