PCI卡上内存寻址的问题（如能答疑，必将送分）

假如板卡上总共有2M的内存，通过配置LASxRR向系统申请了两块1M的内存空间。那么请问：
1，在CSxBASE中，可以任意设置这两块内存空间的基址吗？
2，假如在CSxBASE中分别设置了基址，那么上层软件分别访问两块内存空间时，LOCAL BUS端的地址信息是基址＋1M偏移量吗？
举个例子，我可以将这两块内存空间的基址设为4M和8M吗？如果可以的话，LOCAL端是怎么寻址的？
另外，假如在非ISA模式下，能否实现既有端口映射，又有内存映射？

我也想知道，在非ISA模式下只有RD、WR，而MEMRD/CS0、MEMWR/CS1、IORD/USER0、IOWR/USER1是否可用呢？

to bluewind:
你是做硬件的还是作软件的？

忘了说了，我的email是spooling_yang@163.com.qq是17171109，最好加上聊聊。

好像可以任意设，只要基址是范围的倍数就行。

第二个问题还没有解答呀？关键就是它，关系到FPGA内程序的编写。

 

1，在CSxBASE中，可以任意设置这两块内存空间的基址吗？
2，假如在CSxBASE中分别设置了基址，那么上层软件分别访问两块内存空间时，LOCAL BUS端的地址信息是基址＋1M偏移量吗？

　1、不可以。基址必须是范围的倍数或0，且基址＋范围还不能超出你定义的一个或多个地址空间的范围。
　2、是这样。

 

举个例子，我可以将这两块内存空间的基址设为4M和8M吗？如果可以的话，LOCAL端是怎么寻址的？

　　LOCAL端的寻址是靠你自己设计的局部端的译码器实现的，与基址、范围等没有关系，因为那都是为PCI－＞局部寻址准备的。
 

另外，假如在非ISA模式下，能否实现既有端口映射，又有内存映射？

　　可以呀，把SPACE0~SPACE3和EXPROM可以映射到内存空间或I/O空间，这由你来决定。仔细看看DATASHEET中第8章中有关内容。

这是我的理解，不对请指正！

首先感谢诸位关心，问题已解决。出现这个疑问的原因是在与一位朋友通电话时出现理解错误，现在我把正确的理解告诉大家。

1，基址首先是偏移量的整数倍（0也是整数），满足这个条件，基址可在256M范围内任意选择。
2，LOCAL BUS端的地址信息只是偏移量的大小，同时相应的CSx#变为低电平！换句话说，假如CS0BASE分配了1M的RANGE，那么，如果访问它，LOCAL端的A[19..0]参与译码，不用管基址，同时CS0#变为低电平。在具体使用时，CSx#应与ADS#同时使用。
3，在非ISA模式下，可以实现既有端口映射，又有内存映射！

我想诸位的理解应该是与我一样的，只是表达方式不同。现在将分分给大家，感谢大家百忙之中抽出时间来帮我答疑。

你的问题好象不是PCI的,而是你特定的芯片.
对于PCI来说,基址放在配置寄存器内,如果你的卡支持PnP,那么基址寄存器的值是由驱动动态分配的,如果你分两次分配1M的内存,那么可能他们不连续.通常使用时,你不需要考虑基址(PCI BUS DRIVER已经为你做好了),只要考虑偏移就可以了.

 

在具体使用时，CSx#应与ADS#同时使用。

    怎么理解这句话呢？

1，我说的基址是PCI寄存器分配的，不是指系统分配的。
2，确切的说，CSx#决定基址，也就是板卡上哪一块空间，ADS#是地址偏移量变化的发起信号。都是访问1M内存，你怎么知道是哪一块的呢？就靠CSx#来判断。ADS#的用法可以看时序图。

哥们，我只是回了一句话，你就送分了，受之有愧啊!
下面是我和plx的工程师联系时，他回复的mail中的部分内容，管它有用没用，借你的地方贴上它，也许对后人有帮助。

                                 PLX信件
              info@plxtech.com

  技术支持：


My name is Hogan Lee.  I am the senior field applications engineer for China based in US.  Please see application notes on how to covert ISA logic using PCI 9052 vs PCI 9050.  PCI 9052 has the ISA glue logic built into the chip.  Attached please find PCI9052 RDK lite manuals with schematics and pal equations.

Please contact our distributor to register your project so I can continue supporting you in the future.

Best Regards,

-Hogan
At 09:48 AM 7/16/2002 -0700, you wrote:

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How to set up the 9052 to work with a specific ISA card. Most problems occur with the setting of the various registers.

The 9052 uses a process called re-mapping to map an ISA card into PCI space.During the boot procedure the BIOS effectively reads the amount of memory or I/O space requested by the 9052 and allocates this within the PCI memory map. The base address of the various regions are written back into the PCIBAR registers.

When using the 9052 in ISA mode local address space 0 is used for memory accesses and local address space 1 is used for I/O space accesses. Thus in order to allocate the correct amount of memory you have to know the amount
of memory and/or I/O space required by your card (called the range) and place the inverse of this value in the appropriate LASxRR register. Because the range for a local address space must be a power of 2 you may have to round up the value to ensure that sufficient memory is allocated.

It should also be noted that because local address space 1 is to be used for I/O accesses the least significant bit of the LAS1RR register must be set to 1.

The next thing we need to do is to set the base address registers. Your ISA card will have a memory and/or I/O base address. This is the address we need to set up in the LASxBA registers. Once again the base address for memory
accesses is placed in the LAS0BA register and the base address for I/O access should be placed in the LAS1BA register.

There are a couple of points to note about the local base address registers.The first is that the register has to have bit 0 set to 1 if the space is to be enabled and mapped into PCI space. Secondly, the base address used has to be a multiple of the range or 0. This restriction may require that the base address is lowered and the range increased to ensure that the ISA base and range of your card are covered.

In addition to setting the local address base and range registers, we also have to set the chip select registers. Chip select zero must be set so that it maps directly over the local address space 0 and chip select one must be set
to map over local address space 1.

Figuring out how to program the CSxBASE registers always seems to cause confusion. There are several descriptions on how to do this posted in the data books and on the web site. There is also an Excel97 spreadsheet to assist with this. For occasional use the simplest method is to write the
powers of 2 down on a sheet of paper place 1\'s in the appropriate places and then convert this to a hex number. To work in this way place a 1 in bit 0 (to enable the chip select), place a 1 in the column immediately to the
right of the range required and place another 1 in the appropriate column for the base address. For example, if you wanted a chip select with a range of 16 bytes and a base address of 0x100 then the table would look like this;

...1024 512, 256 128 64 32, 16 8 4 2 1
... 0    1    0   0   0  0   0 1 0 0 1

Thus the CSxBASE register would be 0x00000109.

Okay, so after all the explanation let\'s try an example. Assume that your ISA card requires 1kbytes of memory space which starts at address 0x1000 on the ISA bus and 16 bytes of I/O space starting at address 0x308.

Starting with the memory space first, LAS0RR must be set to the inverse of the 1K bytes. 1K is 0x3ff, the inverse is 0xfffffc00 and this is the number we put into LAS0RR.

Looking at the base address required (0x1000) we can see that this is a multiple of the range so we do not need to modify it or the range. Thus the LAS0BA register is set to 0x00001001 - remember that we have to set the least significant bit to 1 to enable the local address space.

For the I/O space things are a little more complicated. If we look at the base address, it is not a multiple of the range. Therefore to ensure that the I/O space of the card is covered we will have to reduce the base address value and increase the range to compensate (As an aside, when re-designing your card, you may be able to reduce or remove the decoding such that the base address starts at 0. This would of course simplify the register settings and the design considerably).

Let\'s lower the base address to 0x300. Therefore the LAS1BA register must be set to 0x00000301.

To ensure that the cards I/O range is covered (0x308 to 0x317) we increase the range to 32 bytes i.e. 0x1f. Therefore the LAS1RR register is set to 0xffffffe1. The 1 in the least significant bit is set because local address
space 1 is mapped into I/O space.

Now that we have the values for the base address and range registers we can set up the chip select registers. The CS0BASE register has to be set to cover the memory mapped region in local address space 0. Based on the method
described above the CS0BASE register value should be 0x00001201. Similarly the CS1BASE register has to cover the I/O mapped region set up in local address space 1. The value for CS1BASE should be 0x00000311.

Unfortunately, we are not quite finished yet. We also have to set up the bus region descriptor registers to select either 8 or 16 bit operation depending on whether your ISA card is an 8 or 16 bit card. Thus LAS0BRD and LAS1BRD
have to be set to either 0x00000002 for 8 bit operation or 0x00400002 for 16 bit operation.

We also have to ensure that the CNTRL register is set to the correct value.This should be set to 0x007X0X12 where X = don\'t care although you may want to set these to specific values for your application. Alternatively, you can switch on the PCI 2.1 Mode i.e.CNTRL[14]=1 in which case CNTRL[22:19] will be don\'t cares.

The INTCSR register should be set to 0x1XXX, The 1 in bit 12 is actually the enable for the ISA bus mode so it\'s critical if you want to use the local bus as an ISA bus. If you want to have interrupts then you will have to enable the appropriate local interrupts in the INTCSR register and also enable the PCI interrupt (INTCSR[6]). Interrupts are handled rather differently under PCI to ISA. On ISA cards you used jumpers to select the appropriate IRQ for your application, whereas in PCI there is only one interrupt - INTA# - which is shared between all single function PCI devices.

You should route the IRQ from your ISA card to one of the LINTi pins on the 9052. Once the INTCSR register has been enabled then the assertion of the local interrupt will generate the INTA#.


One other thing to note is that you should add a pull up or pull down resistor on the LINTix pins. This resistor should pull the interrupt to its inactive state thereby ensuring that an interrupt isn\'t generated before the driver is loaded.

As noted above INTCSR[12] determines if the device is in ISA mode or not. A quick look at the data book shows that this bit can only be loaded via the EEPROM. It is therefore essential that an EEPROM is connected to the 9052 if you are going to use the ISA interface. In fact, because the BIOS has to determine how much PCI memory and I/O space is required for each device during boot, you have to program the local registers as well. So all of the values we mentioned above have to be programmed into the EEPROM before the system will boot with the values we require.

Rather curiously the sense of the reset is different between the PLX standard local bus modes (C and J modes) and the ISA mode. Thus, because ISA mode is only selected when the EEPROM is loaded, the reset output (LRESET#) may initially be high. It will go low once the INTCSR register is loaded from the EEPROM.

How do we access our ISA bus?

If you run a debugging program such as PLXMon then you will see that various numbers have been placed in the PCIBAR registers of the 9052. PCIBAR 0 and 1 are the addresses of the 9052 in PCI memory space and PCI I/O space respectively. These addresses can be used to access the registers of the 9052 itself. However, the registers which we need to look at before accessing our ISA bus are PCIBAR 2 and 3.


PCIBAR 2 is the address in PCI memory space which is mapped to the ISA memory space of our card. PCIBAR 3 is the address in PCI I/O space which is mapped to the ISA I/O space of our card.

If we take the example we used before i.e.
Local address space 0 = memory mapped from 0x00001000 to 0x000011ff
Local address space 1 = I/O mapped from 0x00000300 to 0x0000031f


Suppose that the BIOS places the following values in the PCIBARs;

PCIBAR2 = 0xffcf0000
PCIBAR3 = 0x0000fc01

then an access at address 0xffcf0014 will result in an access on the local bus at location 0x00001014.

The I/O space is a little more complicated. First the least significant bit in PCIBAR3 is just used to show that this location exists in I/O space. So the real base address is 0x0000fc00, not 0x0000fc01.

Secondly, in our original example had to lower the base and increase the range of the I/O region because the original base address was not a multiple of the range. Our I/O region for our ISA device was from 0x308 to 0x317. So to write to the lowest I/O location in our card we have to take a little care. An access to location 0x0000fc08 will map to location 0x308 on the local bus.

Hopefully the above has cleared up a few queries regarding the register settings on the 9052. If you are still having difficulties then please do not hesitate to contact me.

分数是小问题，主要是找个机会大家交流一下。多发几篇帖子分数不就回来了，是不是？关键在于交流中能不能有所提高。你的英文资料也很好呀，有机会我仔细的看一下。不过我现在是使用NON-ISA模式的。

CSxBA不能随便写，基址必须包含寻址范围，比如：
1M的寻址范围，基址必须是1M乘上2的N次方，N为自然数，N>=1 。
不然不能正确使用CSx# 。
所以LASxBA 也必须做相应的调整，
LASxRR , LASxBA ,CSxBA 他们三个必须匹配。