EOT#有效后，9054的响应。

别告诉我去看DATASHEET,我看了N遍，觉得里面的问题很严重，一定是写错了。才不得已POST.
清详细说明，越详细越好。比如在BLAST#使能的情况下，.....在BLAST#不使能的情况下.......。谢谢了。

老大们，帮帮忙吧。

我看过很多遍了,觉得没什么问题.你说的问题在哪里?

End of Transfer (EOT#) Input

The DMA EOT# Enable bit(s) (DMAMODE0[14] and/or
DMAMODE1[14]) determines the number of Lwords to
transfer after a DMA controller asserts EOT# input.
EOT# input should be asserted only when the PCI
9054 owns a bus.
If BLAST# output is not required for the last Lword of
the DMA transfer (DMAMODE0[15]=1 and/or
DMAMODE1[15]=1), the DMA controller releases the
data bus and terminates DMA after it receives an
external READY#. Or, the internal wait state counter
decrements to 0 for the current Lword. If the DMA
controller is currently bursting data that is not the last
Data phase for the burst, BLAST# output is not
asserted.
If BLAST# output is required for last Lword of the DMA
transfer (DMAMODE0[15]=0 and/or DMAMODE1[15]=0),
the DMA controller transfers one or two Lwords,
depending on the Local Bus width. If EOT# is asserted,
the DMA controller completes the current Lword and one
additional Lword (this allows BLAST# output to be
asserted during the final Lword). If the DMA FIFO is full or
empty after the Data phase in which EOT# is asserted,
the second Lword is not transferred.

EOT enable bit愣决定EOT有效之后的反应，这不是显然错了吗？我觉得应该改成The Fast/Slow Terminate Mode Select bit(s)
(DMAMODE0[15] and/or DMAMODE1[15])来决定。

老大，是不是错了？

好像是有些问题,老兄看的够仔细的,找PLX的技术支持联系一下.

没找过，如何找？谢谢。