vhdl 256进制高阻态无法实现

这是我的一个256进制记数器,可以通过运行.但是我想在hs为1时让输出的abl8为高阻态,可是结果总是为0,不知道是什么原因,请帮忙!


----------------------------------------------------------
--counter for low address
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counterl8 IS
PORT(llc2:IN STD_LOGIC;
         hs:IN STD_LOGIC;
abl8:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END counterl8;
ARCHITECTURE counterl8_behave OF counterl8 IS
SIGNAL tempvec:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
  PROCESS(llc2,hs)
BEGIN
IF(hs=\'1\')THEN
tempvec<=\"ZZZZZZZZ\";
END IF;
IF(hs\'EVENT AND hs=\'0\')THEN
 tempvec<=\"00000000\";
END IF;
IF(llc2\'EVENT AND llc2=\'1\')THEN
IF(hs=\'0\')THEN
tempvec<=tempvec+1;
END IF;
ELSE
tempvec<=tempvec;
END IF;
END PROCESS;
  abl8<=tempvec;

END counterl8_behave;
多谢!

--counter for low address
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY  counterl8 IS
PORT(llc2:IN STD_LOGIC;
hs:IN STD_LOGIC;
abl8:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END  counterl8;
ARCHITECTURE  counterl8_behave OF  counterl8 IS
SIGNAL tempvec:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(llc2,hs)
BEGIN
--IF(hs=\'1\')THEN
--tempvec<=\"ZZZZZZZZ\";
--END IF;
IF(hs\'EVENT AND hs=\'0\')THEN
tempvec<=\"00000000\";
END IF;
IF(llc2\'EVENT AND llc2=\'1\')THEN
IF(hs=\'0\')THEN
tempvec<=tempvec+1;
END IF;
ELSE
tempvec<=tempvec;
END IF;
END PROCESS;
abl8<=tempvec when hs=\'0\' else \"ZZZZZZZZ\";
END  counterl8_behave;

还想问一下,我的那种做砝为什么不出错,可是结果不对,还有,这两种做法的主要区别是什么呢?等我调试一下,通过了就送你分,呵呵!