FIFO的原代码---具有通用性

timescale 1ns/1ns
module FIFO_SYNC(RST, CLK, DIN, DOUT, WEN, REN, OE, EF, FF);
parameter DATA_WIDTH = 16;
parameter FIFO_DEPTH = 4;
`define D_WIDTH 16
`define F_DEPTH 4

input RST, CLK, WEN, REN, OE;
input [DATA_WIDTH-1:0] DIN;
inout [DATA_WIDTH-1:0] DOUT;
output EF, FF;


reg [DATA_WIDTH-1:0] SF_RAM [0:(1<<FIFO_DEPTH)-1]; // (1<<FIFO_DEPTH)-1 = 15
reg [0:(1<<FIFO_DEPTH)-1] WPTR;
reg [0:(1<<FIFO_DEPTH)-1] RPTR;
reg FF_REG, EF_REG;
wire EF_TMP;


// Output Assignment
assign  DOUT = (OE==1'b1)? SF_RAM[RPTR]: `D_WIDTH'bz;
assign  FF = FF_REG;
assign  EF = EF_REG;
// End of Output Assignment


// FIFO
always @(posedge CLK)
begin
   if(WEN==1'b1 & FF_REG==1'b0)
               SF_RAM[WPTR] <= DIN;
end
//Write Pointer
always @(posedge CLK or posedge RST)
begin
if(RST==1'b1)
       WPTR <= `F_DEPTH'b0;
else
   begin
     if(WEN == 1'b1 & FF_REG == 1'b0)
       if(WPTR == `F_DEPTH'b1111)
               WPTR <= `F_DEPTH'b0;
       else
               WPTR <= WPTR + 1'b1;
  end
end
//Read Pointer
always @(posedge CLK or posedge RST)
begin
if(RST==1'b1)
       RPTR <= `F_DEPTH'b1111;
else
   begin
     if(REN == 1'b1 & EF_REG == 1'b0)
       if(RPTR == `F_DEPTH'b1111)
               RPTR <= `F_DEPTH'b0;
       else
               RPTR <= RPTR + 1'b1;
   end
end
//Full Flag
always @(posedge CLK or posedge RST)
begin
if(RST==1'b1)
       FF_REG <= 1'b0;
else
   begin
     if(WPTR == RPTR & WEN == 1'b1 & REN == 1'b0)
               FF_REG <= 1'b1;
     else if(FF_REG == 1'b1 & REN == 1'b1)
               FF_REG <= 1'b0;
   end
end
//Almost Empty
assign EF_TMP = ((RPTR == WPTR-1'b1)|
                (RPTR == `F_DEPTH'd15 & WPTR == `F_DEPTH'd1)|
                (RPTR == `F_DEPTH'd14 & WPTR == `F_DEPTH'd0))? 1'b1 : 1'b0;
//Empty Flag
always @(posedge CLK or posedge RST)
begin
if(RST==1'b1)
       EF_REG <= 1'b1;
else
   begin
     if(EF_TMP == 1'b1 & WEN == 1'b0 & REN == 1'b1)
               EF_REG <= 1'b1;
     else if(EF_REG == 1'b1 & WEN == 1'b1)
               EF_REG <= 1'b0;
   end
end
endmodule