十万火急，小弟给分啊！！

制作电子数字钟，由一个24进制带进位位计数器和两个60进制带进位位计数器组成电路原理图编译时出错。Node missing scour:clk
检查接线没有错误的呀！

望各位大虾指点。谢谢。
 在线等啊，帮忙啊，好心人！

你检查你的原理图中给的pcb
封装是否与pcb库中的管脚对应一致。

  谢谢楼上的，很感谢，我检查下，可以和你交流一下么？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port( clk: in std_logic;
C,B,A: out std_logic);
end fenpin;
architecture fenpin_arch of fenpin is
signal count:std_logic_vector (2 downto 0);
begin
process (clk)
begin
if clk=\'0\' then
count<=count+\'1\';
end if;
end process;
A<=count(0);
B<=count(1);
C<=count(2);
end fenpin_arch;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count24 is
port(clk,clr,en:in std_logic;
A0,B0,C0,D0ut std_logic;
A1,B1,C1,D1ut std_logic);
end count24;

architecture count24_architecture of count24 is

signal count0:std_logic_vector(3 downto 0);
signal count1:std_logic_vector(1 downto 0);
Begin
A0<=count0(0);
B0<=count0(1);
C0<=count0(2);
D0<=count0(3);
A1<=count1(0);
B1<=count1(1);
C1<=\'0\';
D1<=\'0\';
process(clk,clr,en)
Begin
if (clr=\'1\') then
count0<=\"0001\";
count1<=\"00\";
elsif clk=\'0\' and en=\'1\' then
if (count0=\"0100\" and count1=\"10\")then
count0<=\"0001\";
elsif(count0=\"1001\")then
count0<=\"0000\";
else
count0<=count0+\'1\';
end if;
if (count0=\"0100\" and count1=\"10\")then
count1<=\"00\";
elsif count0=\"1001\" then
count1<=\"01\";
end if;
end if;
end process;
end count24_architecture;