阅读:2149回复:10
68013 AUTOIN 问题!向做过的朋友求助!50f
方案是 68013+CPLD+AD
RDY信号触发一次就自动写一个16bit数据到FIFO里 现在CPLD产生若干次RDY0低电平脉冲,同时数据出现在总线上, 程序里设了AUTOIN,可批量读数据总是无法返回,郁闷好久了 还有设了AUTO模式后,读写时T_poll()函数不会被调用吧?? 诚心向做过的朋友请教! |
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沙发#
发布于:2004-11-06 18:19
可能的原因:
1,没有片选上68013,估计是数据出现在数据线上也没有用 2,没有选择端点(FIFOADDR[0:1]),因此数据不知道写到哪里去了 3,没有给出slwr信号(或者slrd信号,记不清了),因此数据没写到端点里去 4,端点的AUTO模式设置的不对,也就是说设置可能没有生效 最后,即使设置了AUTO模式,TD_Poll()函数还是会被调用的,只是此时它是个空函数而已, 当然你也可以把这个函数从主程序中注释掉,此时它是不起作用。 建议你好好看看Auto模式的时序吧。 |
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板凳#
发布于:2004-11-07 16:36
首先谢谢 jinghuiren 的回复!你在这方面很有经验,帮助过很多后来者,请再关心一下,帮我度过难关。
我用的是56pin的片子,GPIF模式,在例子FX2_to_extsyncFIFO GPIF FIFO Transactions Auto mode 上修改的,Rdy0信号正常 配置端点: EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit SYNCDELAY; EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops SYNCDELAY; EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops SYNCDELAY; GpifInit (); // initialize GPIF registers SYNCDELAY; EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag SYNCDELAY; EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag SYNCDELAY; 这里有疑问: 1.AUTO模式何时触发GPIF波形??还是GPIF一直在几个状态里跑,满足条件就读写数据?? 2.GPIF波形怎么区分数据是要读还是要写? 3.56Pin的片子 TCXpire 信号还有用吗?? 看到你正在线 :) |
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地板#
发布于:2004-11-08 13:54
自己先顶了,
GPIF 波形怎么知道我要用在哪个端点呢? 疑惑中 ... |
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地下室#
发布于:2004-11-09 11:15
我上面说的是Slave FIFO模式的
GPIF没做过,但类似,你好好看看关于GPIF的章节吧 我帮不上忙了 很遗憾。 |
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5楼#
发布于:2004-11-09 11:23
我也做这个相关,不过我打算用手动,自己写代码将2过来的数据转换到6端点后输入PC
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6楼#
发布于:2004-11-09 13:47
如果你得AD速度不高,应该没有问题得
昨晚这样试了发现 READYSTATE 判断不过 难道我给得RDY0有问题?? |
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7楼#
发布于:2004-11-10 13:04
我也使用的68013+CPLD+TLC5540 实现40M采样,以开发成功,我是在CY的可视化GPIF工具里FIFO列子基础上修改成的..你可以参考一下,相信一定回解决的 ;)
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8楼#
发布于:2004-11-10 15:56
谢谢你,朋友
我也是改的FIFO例子 检测GPIFREADYSTAT能得到信号,可GPIF总不触发读数据 加了的检测 if(RDY0==1 or FifoFlag==1) => idle else => s1 (read bus,addr++) 难道理解有误吗,还请你能给我点启示啊,兄弟 怎么送分?一并告诉我啊 |
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9楼#
发布于:2004-11-12 12:29
再顶下先,liwenxin201 网友请支持,问题太奇怪了,实在难以理解
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10楼#
发布于:2004-11-16 22:33
现发给源码如下:
void TD_Init(void) // Called once at startup { // set the CPU clock to 48MHz CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); SYNCDELAY; REVCTL = 0x02; // REVCTL.1=1; use "dynamic OUT automaticity" SYNCDELAY; // see TRM section 15.14 EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered SYNCDELAY; EP4CFG = 0x00; // EP4 not valid SYNCDELAY; EP6CFG = 0xe0; // EP6IN, bulk, size 512, 4x buffered SYNCDELAY; EP8CFG = 0x00; // EP8 not valid SYNCDELAY; OEA=0xFF; OEA=0xFF; FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host SYNCDELAY; FIFORESET = 0x02; // reset EP2 FIFO SYNCDELAY; FIFORESET = 0x06; // reset EP6 FIFO SYNCDELAY; FIFORESET = 0x00; // clear NAKALL bit to resume normal operation SYNCDELAY; EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit SYNCDELAY; EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, word ops SYNCDELAY; EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, word ops SYNCDELAY; EP6AUTOINLENH=0x02; SYNCDELAY; EP6AUTOINLENL=0x00; SYNCDELAY; GpifInit (); // initialize GPIF registers SYNCDELAY; EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag SYNCDELAY; EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag SYNCDELAY; // global flowstate register initializations FLOWLOGIC = FlowStates[19]; // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 (FIFO Flag) SYNCDELAY; FLOWSTB = FlowStates[23]; // 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe SYNCDELAY; GPIFHOLDAMOUNT = FlowStates[26]; // hold data for one half clock (10ns) assuming 48MHz IFCLK SYNCDELAY; FLOWSTBEDGE = FlowStates[24]; // move data on both edges of clock SYNCDELAY; FLOWSTBHPERIOD = FlowStates[25]; // 20.83ns half period SYNCDELAY; // OEA |= 0x01; // turn on PA2 as output pin // IOA |= 0x01; // pull PA2 high initially // IOA |= 0x01; // bring PA2 low PA0=1; PA0=1; PA1=1; PA2=1; PA3=0; //Ñ¡Ôñ?ÖƵ±È PA4=0; PA5=0; PA6=0; } void TD_Poll(void) { if(in_enable) // if IN transfers are enabled { if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE { if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full { if(enum_high_speed) { SYNCDELAY; GPIFTCB1 = 0x02; // setup transaction count (512 bytes/2 for word wide -> 0x0100) SYNCDELAY; GPIFTCB0 = 0x00; SYNCDELAY; } else { SYNCDELAY; GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20) SYNCDELAY; GPIFTCB0 = 0x40; SYNCDELAY; } SYNCDELAY; EP6GPIFTCH = 0x02; SYNCDELAY; EP6GPIFTCL = 0x00; // trigger FIFO read transaction(s), using SFR // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s) Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation SYNCDELAY; GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO SYNCDELAY; // while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit // { // ; // } //SYNCDELAY; } } } } GPIF 代码如下: // GPIF Waveform 2: FIFO Rea // // Interval 0 1 2 3 4 5 6 Idle (7) // _________ _________ _________ _________ _________ _________ _________ _________ // // AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val // DataMode Activate Activate Activate Activate Activate Activate Activate // NextData NextData NextData NextData NextData NextData NextData NextData // Int Trig No Int No Int No Int No Int No Int No Int No Int // IF/Wait Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 // Term A RDY0 // LFunc AND // Term B RDY0 // Branch1 Then 1 // Branch0 ElseIdle // Re-Exec Yes // Sngl/CRC Default Default Default Default Default Default Default // CTL0 1 1 1 1 1 1 1 1 // CTL1 0 0 0 0 0 0 0 0 // CTL2 0 0 0 0 0 0 0 0 // CTL3 0 0 0 0 0 0 0 0 // CTL4 0 0 0 0 0 0 0 0 // CTL5 0 0 0 0 0 0 0 0 // // END DO NOT EDIT // DO NOT EDIT ... // // GPIF Waveform 3: FIFO Wri // // Interval 0 1 2 3 4 5 6 Idle (7) // _________ _________ _________ _________ _________ _________ _________ _________ // // AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val // DataMode Activate Activate Activate Activate Activate Activate Activate // NextData SameData SameData SameData SameData SameData SameData SameData // Int Trig No Int No Int No Int No Int No Int No Int No Int // IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 // Term A // LFunc // Term B // Branch1 // Branch0 // Re-Exec // Sngl/CRC Default Default Default Default Default Default Default // CTL0 1 1 1 1 1 1 1 1 // CTL1 0 0 0 0 0 0 0 0 // CTL2 0 0 0 0 0 0 0 0 // CTL3 0 0 0 0 0 0 0 0 // CTL4 0 0 0 0 0 0 0 0 // CTL5 0 0 0 0 0 0 0 0 // // END DO NOT EDIT // GPIF Program Code // DO NOT EDIT ... #include "fx2.h" #include "fx2regs.h" #include "fx2sdly.h" // SYNCDELAY macro // END DO NOT EDIT // DO NOT EDIT ... const char xdata WaveData[128] = { // Wave 0 /* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, /* Opcode*/ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, /* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, // Wave 1 /* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, /* Opcode*/ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, /* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, // Wave 2 /* LenBr */ 0x01, 0x8F, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, /* Opcode*/ 0x06, 0x07, 0x06, 0x06, 0x06, 0x06, 0x06, 0x02, /* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, // Wave 3 /* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, /* Opcode*/ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, /* Output*/ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, }; // END DO NOT EDIT // DO NOT EDIT ... const char xdata FlowStates[36] = { /* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, }; // END DO NOT EDIT |
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