xilinx 高分紧急求救

我在设计中用了XILINX里面的一个CLKDLL的东西，结果编译老通不过。错误提示是：  

CLKIN pin of CLKDLL symbol "xlxi_533" is driven by pin O of IBUFG
   symbol "xlxi_540" (output signal=xlxn_208). Proper phase relationship to the
   original clock cannot be guaranteed if the driver is not an IBUFG or BUFG.
Timing analysis results may not be valid. If BUFG is used, it must also be
   driven by the same DLL. To by-pass this check, set environment variable
   XIL_MAP_ALLOW_ANY_DLL_INPUT.
ERROR:LIT - CLKFB pin of CLKDLL symbol "xlxi_533" is driven by pin CLK270 of
   CLKDLL symbol "xlxi_533". Proper phase relationship to the original clock
   cannot be guaranteed if the driver is not an IBUFG or BUFG. Timing analysis
   results may not be valid. If BUFG is used, it must also be driven by the same
   DLL. To by-pass this check, set environment variable
   XIL_MAP_ALLOW_ANY_DLL_INPUT.

如果按照提示应该设置环境变量XIL_MAP_ALLOW_ANY_DLL_INPUT 可是设置值是多少？在哪设置？还是别的问题？
盼高人指点

[编辑 -  12/17/04 by  yxbupt]

太简单还是太难？难道真的没人知道么？