请Verilog高人指点寄存器的这两行设计代码

请Verilog高人指点寄存器的这两行设计代码


各位高人：
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我的代码实际上要实现循环移位的操作，我是这样写的：
reg[1:128] data;
...
data[1:128] <= { data[64:128],data[1:63] };

但在综合的报告中列出了一大串的这样的信息，
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd4 has been replicated 1 time(s)
FlipFlop state_FFd3 has been replicated 6 time(s)
FlipFlop state_FFd4 has been replicated 13 time(s)
FlipFlop state_FFd1 has been replicated 5 time(s)

倒不是错误，但是特别多！上面的这一写法不如
new_data[1:128] <= { data[64:128],data[1:63] };
这样的写法，而且综合后的频率还比前面的那一句要高。


是不是data[1:128] <= { data[64:128],data[1:63] };这种写法不好？但是经典的a <= a+1;这样的写法呀？

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请高人指教！我不胜感激！
Right here waiting!

看不明白什么意思？